Specifications

PK2100 Series Z-World 530-757-3737 7
Baud Rates
The Z180 serial ports can generate standard baud rates. When
the clock is 6.144 MHz, rates range from 150 to 38.4 kHz. When
the clock is 9.216 MHz, rates range from 75 Hz to 19.2 kHz.
LCD
The 2×20 LCD used with the PK2100 can come from one of sev-
eral vendors. All the LCDs are identical in operation, electrical
connections, and dimension. They may differ in timing.
An LCD can take up to 1600 µs to carry out an operation.
Therefore it provides a busy flag, which you may read at ad-
dress LCDRD (0xD0). It is an error to send other commands or
data to an LCD while it is busy.
To communicate with the LCD, send commands to address
LCDWR (0xD8). Command values are built into the command.
To write data to the LCD, use address LCDWR+1. To read data
from the LCD, except for the busy flag, use address LCDRD+1.
Refer to any of the LCD manufacturers’ data sheets for infor-
mation regarding LCD operations.
The LCD connector is a 2×7 header, P2.
Keypad
To read the 2×6 matrix keypad, you “drive” the row or rows
you wish to sample, then read the columns. Any or all keys
may be sensed.
There are four keypad “rows” at addresses KEYR1–KEYR4
(0x86, 0x81, 0x85, 0x87 respectively) and six keypad columns
readable as bits 2–7 of DREG1 (0x81).
The PK2100 can address four keypad rows, but presently there
is support only for 2 keypad rows.
Jumper block J4 uses keypad signals (/KH2, and KV1–KV3) for
operation mode settings.
Beeper
The on-board beeper has two volume levels. Alternately send 1
then 0 to make it oscillate. Write to BEEPH (0x83) for high vol-
ume. Write to BEEPL (0x98) for low volume.
I/O Map
The internal Z180 I/O registers occupy the first 64 (0x40) ad-
dresses of the I/O space. Refer to the Z180 MPU User’s Manual.
The following I/O addresses control the PK2100 devices which
are external to the Z180 processor.
Write Registers
Addr Bit Symbol Function
0x80 0
SDA_W EEPROM data, write.
0x81 0
KEYR2 Keypad drive row 2. Open collector, “1”
drives low.
0x82 0 ENB485 Enable RS485 channel
0x83 0
BEEPH Beeper, high-voltage drive. “1” drives
beeper.
0x84 0 SCL EEPROM clock.
0x85 0
KEYR3 Keypad drive row 3. Open collector, “1”
drives low.
0x86 0
KEYR1 Keypad drive row 1. Open collector, “1”
drives low.
0x87 0 KEYR4 Keypad drive row 4. Open collector, “1”
drives low. Also, tenth high-current output
(
DRV10) if key row not used.
0x88
0–7 UEXP Internal DAC, bits 9-2. See also UEXPA and
UEXPB below.
0x90 0–7
DAC External DAC, bits 9-2. See also DACA and
DACB below.
0x98 0 BEEPL Beeper, low-voltage drive drive. “1” drives
the beeper.
0x99 0
DRV1 Digital output 1. “1” drives output.
0x9A 0
DRV2 Digital output 2. “1” drives output.
0x9B 0
DRV3 Digital output 3. “1” drives output.
0x9C 0
DRV4 Digital output 4. “1” drives output.
0x9D 0
DRV5 Digital output 5. “1” drives output.
0x9E 0
DRV6 Digital output 6. “1” drives output.
0x9F 0
DRV7 Digital output 7. “1” drives output.
0xA0 0
UEXPA Internal DAC, bit 1.
0xA1 0
UEXPB Internal DAC, bit 0.
0xA2 0
DACA External DAC, bit 1.
0xA2 0
DACB External DAC, bit 0.
0xA4
0DRV8 Digital output 8. “1” drives output
0xA5
0DRV9 Digital output 9. “1” drives output
0xA6
0RLY1 “1” enables relay 1.
0xA7
0RLY2 “1” enables relay 2.
0xC8
0–7 BUSADR0 Expansion bus, first address byte
0xCA
0–7 BUSADR1 Expansion bus, second address byte
0xCC
0–7 BUSADR2 Expansion bus, third address byte
0xCE
0–7 BUSWR Expansion bus write to port
0xD8
0–7 LCDWR LCD write register, control
0xD9
0–7 LCDWR+1 LCD write register, data
OxE0
0–3RTRW Real time clock, read/write data registers
0xF0
0–3 RTALE Real time clock, write address latch
Read Registers
Addr Bit Symbol Function
0x80
0–7 UINP Bits 0–6 are universal inputs 0–5 and the
high-gain analog input (bit
6). Bit 7 is PR, a
user-programmable jumper (J8 pins 11-12)
and is low when the jumper is installed.
0x81
0–7 DREG1 Bit 0 is EEPROM data bit. Bit 1 is NMI inter-
rupt line (power fail line). Bits 2–7 are key-
pad columns
0–5.
0x88 0–7 DREG2 Bits 0–6 are digital inputs 0–6. Bit 7 is the
universal input channel fed through AD+ (or
universal input channel
8).
0x98 — WDOG Reading this location “hits” the watchdog
timer.
0xC0 0–7 BUSRD0 First read, data port of expansion bus
0xC2 0–7 BUSRD1 Second read, data port of expansion bus
0xC4
0–7— Unused bus read address
0xC6 — BUSRESET Read this location to reset all devices on the
expansion bus.
0xD0 0–7 LCDRD LCD read register, control
0xD1 0–7 LCDRD+1 LCD read register, data