User`s manual

32 RabbitCore 2000
The values from the table above are derived using 55 ns (25.8 MHz version) and 90 ns
(18.4 MHz version) memory access times. External capacitive loading can be improved
by 10 pF for commercial temperature ranges, but do not exceed 100 pF. See the AC tim-
ing specifications in the Rabbit 2000 Users Manual for more information.
Figure A-3 shows a typical timing diagram for the Rabbit 2000 microprocessor memory
read and write cycles.
Figure A-3. Memory Read and Write Cycles
T
adr
is the time required for the address output to reach 0.8 V. This time depends on the
bus loading. A0 has a stronger driver and can handle larger capacitive loads than the other
address lines. T
setup
is the data setup time relative to the clock. Tsetup is specified from
30%/70% of the V
DD
voltage level. Add 1.5 ns to T
adr
for each 10 pF of additional bus
loading above 70 pF.
T
adr
T
adr
Memory Read (no wait states)
/WE
T
hold
valid
CLK
A[19:0]
D[7:0]
valid
T
setup
T
hold
Memory Write (no extra wait states)
CLK
A[19:0]
D[7:0]
/CSx
valid
/OEx
/CSx
valid
/WEx
valid
T1
T2
T1
Tw
T2
valid