User`s manual

User’s Manual 11
2.3 Memory I/O Interface
Thirteen of the Rabbit 2000 address lines (A0–A12) and all the data lines (D0–D7) are
available as outputs on the RabbitCore 2000. I/0 write (/IOWR), I/0 read (/IORD), buffer
enable (/BUFEN), and Watchdog Output (/WDO) are also available for interfacing to
external devices.
The STATUS output has three different programmable functions:
1. It can be driven low on the first op code fetch cycle.
2. It can be driven low during an interrupt acknowledge cycle.
3. It can also serve as a general-purpose output.
The output clock is available on the PCLK pin. The primary function of PCLK is as a
peripheral clock or a peripheral clock ÷ 2, but PCLK can instead be used as a digital out-
put. PCLK can also be disabled by removing R27 if there is a need to reduce radiated
emissions. Removing R27 will disable the PCLK output on pin 19 of header J1.
Figure 5. Location of R27
2.3.1 Additional I/0
Two status mode pins, SMODE0 and SMODE1, are available as inputs. The logic state
of these two pins determines the startup procedure after a reset. /RES_IN is an external
input used to reset the Rabbit 2000 microprocessor and RabbitCore 2000 memory.
/RES_OUT is an output from the reset circuitry that can be used to reset other peripheral
devices.
J1
U11
C16
R37
R38 R40
R41
R42
R39
C17 C18
R14
R19 R20
C12
C13
R26 R25
R24
R22 R21 R23 C10
C11
R13
D11 R11 R12D12
R18
R15
R28
R29
R30
Q14
R31
D10Q11Q10R10
R16
R17
JP2
Q15 D13
C15
R33
R36
R32
R34
R35
U10
C14
R27
Flash
EPROM
Q12
Q13
A12
A6
A4
A2
A0
PC0
PC2
PC4
PC6
PD0
PD2
PD4
PD6
GND
VBAT
SM0
/RESO
VCC
A10
A8
GND
/RSTI
SM1
VRAM
VCC
PD7
PD5
PD3
PD1
PC7
PC5
PC3
PC1
STAT
A1
A3
A5
A7
A9
A11
VCC
PA1
PA3
PA5
PA7
PB1
PB3
PB5
PB7
GND
D6
D4
D2
D0
/WDO
/IOR
PE0
PE2
PE4
PE6
/BEN
/IOW
PE1
PE3
PE5
PE7
D1
D3
D5
D7
PCLK
PB6
PB4
PB2
PB0
PA6
PA4
PA2
PA0
GND
R27
Bottom Side