User`s guide

55 | P a g e
DC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V
Operating Conditions
Temperature Range
CA555, LM555 . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CA555C, LM555C, NE555 . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W)
Metal Can Package . . . . . . . . . . . . . . . 170 85
PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A
SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A
Maximum Junction Temperature (Hermetic Package) . . . . . . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and
operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications TA = 25oC, V+ = 5V to 15V Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS
CA555, LM555 CA555C, LM555C, NE555
MIN TYP MAX MIN TYP MAX UNITS
DC Supply Voltage V+ 4.5 - 18 4.5 - 16 V
DC Supply Current (Low State),
(Note 2)
I+ V+ = 5V, RL = - 3 5 - 3 6 mA
V+ = 15V, RL = - 10 12 - 10 15 mA
Threshold Voltage VTH - (2/3)V+ - - (2/3)V+ - V
Trigger Voltage V+ = 5V 1.45 1.67 1.9 - 1.67 - V
V+ = 15V 4.8 5 5.2 - 5 - V
Trigger Current - 0.5 - - 0.5 - A
Threshold Current (Note 3) ITH - 0.1 0.25 - 0.1 0.25 A
Reset Voltage 0.4 0.7 1.0 0.4 0.7 1.0 V
Reset Current - 0.1 - - 0.1 - mA
Control Voltage Level V+ = 5V 2.9 3.33 3.8 2.6 3.33 4 V
V+ = 15V 9.6 10 10.4 9 10 11 V
Output Voltage VOL V+ = 5V, ISINK = 5mA - - - - 0.25 0.35 V
Low State ISINK = 8mA - 0.1 0.25 - - - V
V+ = 15V, ISINK = 10mA - 0.1 0.15 - 0.1 0.25 V
ISINK = 50mA - 0.4 0.5 - 0.4 0.75 V
ISINK = 100mA - 2.0 2.2 - 2.0 2.5 V
ISINK = 200mA - 2.5 - - 2.5 - V
Output Voltage VOH V+ = 5V, ISOURCE = 100mA 3.0 3.3 - 2.75 3.3 - V
High State V+ = 15V, ISOURCE = 100mA 13.0 13.3 - 12.75 13.3 - V
ISOURCE = 200mA - 12.5 - - 12.5 - V
Timing Error (Monostable) R1, R2 = 1kto 100k,
C = 0.1F
Tested at V+ = 5V, V+ = 15V
- 0.5 2 - 1 - %
Frequency Drift with Temperature - 30 100 - 50 - ppm/oC
Drift with Supply Voltage - 0.05 0.2 - 0.1 - %/V
CA555, CA555C, LM555, LM555C, NE555
8-5
Schematic Diagram
Typical Applications
Reset Timer (Monostable Operation)
Figure 1 shows the CA555 connected as a reset timer. In this
mode of operation capacitor CT is initially held discharged by
a transistor on the integrated circuit. Upon closing the “start”
switch, or applying a negative trigger pulse to terminal 2, the
integral timer flip-flop is “set” and releases the short circuit
across CT which drives the output voltage “high” (relay energized).
The action allows the voltage across the capacitor to
increase exponentially with the constant t = R1CT. When the
voltage across the capacitor equals 2/3 V+, the comparator