User`s guide

50 | P a g e
tPLH Clock Clear Set to Output
13 25 ns
Figure 1
VCC = 5.0 PLH pF
tPHL
Clock, Clear, 25 40 ns
CL = 15 F
AC SETUP REQUIREMENTS (TA = 25C)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
tW(H) Clock 25 ns Figure 1
tW(L) Clear, Set 25 ns Figure 2
t
Data Setup Time — HIGH 20 ns
Figure 1
VCC = 5.0 V
ts Data Setup Time — LOW 20 ns
th Hold Time 5.0 ns Figure 1
SN74LS74A
http://onsemi.com
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Figure 1. Clock to Output Delays, Data
Set-Up and Hold Times, Clock Pulse Width
AC WAVEFORMS
*The shaded areas indicate when the input is permitted to change for predictable output performance.
D *
CP
Q
Q
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V 1.3 V
tPLH
tPHL
tPLH
tPHL
th(L)
ts(L) tW(H)
tW(L)
ts(H)
th(H)
1
fMAX
1.3 V
Figure 2. Set and Clear to Output Delays,
Set and Clear Pulse Widths
tW
1.3 V 1.3 V
tW
1.3 V 1.3 V
1.3 V
1.3 V 1.3 V
1.3 V
tPLH tPHL
tPHL tPLH
SET
CLEAR
Q
Q
SN74LS74A
http://onsemi.com
5
PACKAGE DIMENSIONS
1 7
14 8
B
A DIM MIN MAX MIN MAX
INCHES MILLIMETERS