Datasheet

Datasheet

20/34

BD9271KUT

TSZ02201-0F1F0C100260-1-2

27.Feb.2015 Rev.004

www.rohm.com

TSZ22111・15・001

◆Timing chart

●PWM Delay and ON Duty setting procedure

By making register setting, PWM output delay and ON duty time counts of CH1 to CH16 can be controlled.

The above timing chart shows an example for CH1.

(To make delay time count setting, write 06h in address 31h. To make ON duty time count setting, write 07h in address 11h.)

The delay counter starts counting after counting three from the leading edge of VSYNC signal. When the counter reaches the

set delay count value (06h), the duty counter will start counting simultaneously when the PWM_OUT_01 signal is set to “H”.

Subsequently, when the duty counter reaches the set duty count value (07h), the PWM_OUT_01 signal will be set to ”L”.

Since then, the said sequence is continuously repeated.

The same control is also carried out for CH2 to CH16.

The delay counter counts up to FFCh. Even if the set value exceeds this maximum value, it will also count up to FFCh.

●oft-start masking function

A value set at address 10h serves as the pulse number of the VSYNC signal and masks the error signal control in the

relevant section.

(Example) When ADDR10h and DATA02h:

345678

1 2

345678

4093

4094 4095

VSYNC

HSYNC

Delay

counter

Duty

counter

PWM_OUT_01

Figure 17. Setting for PWM Delay and ON Duty

Figure 18. In case of ADDR:10h and DATA:02h