Datasheet
Datasheet
Datasheet
19/34
BD9271KUT
TSZ02201-0F1F0C100260-1-2
© 2013 ROHM Co., Ltd. All rights reserved.
27.Feb.2015 Rev.004
www.rohm.com
TSZ22111・15・001
This register is used to make setting of pulse duty for PWM light modulation in a total of 12 bits, i.e., Bit7-0 when
ADDR11h and Bit3-0 when ADDR12h.
DTY01[11：0] LED Pulse Width
“0000 0000 0000” Normally set to Low (default)
“0000 0000 0001” HSYNC 2 clock width
“0000 0000 0010” HSYNC 3 clock width
“0000 0000 0011” HSYNC 4 clock width
to to
“1111 1111 1100” HSYNC 4093 clock width
“1111 1111 1101” HSYNC 4094 clock width
“1111 1111 1110” HSYNC 4095 clock width
“1111 1111 1111” HSYNC 4096 clock width
The data in register is updated to the newest data when the next PWM signal rises up (positive-edge trigger).
●ADDR=13h～30h
This register is used to make setting of PWM pulse width for LED2 to LED16. The setting procedure is the same as that for
LED1 with ADDR set to 11h and 12h.
The data in register is updated to the newest data when the next PWM signal rises up (positive-edge trigger).
●ADDR=31h
DLYCNT01L (LED1 PWM Delay setting register – Low 8bit-: Read/Write)
Bit 7 6 5 4 3 2 1 0
Register
Name
DLY01[7] DLY01[6] DLY01[5] DLY01[4] DLY01[3] DLY01[2] DLY01[1] DLY01[0]
Default
0 0 0 0 0 0 0 0
The data in register is updated to the newest data when the next VSYNC signal rises up (positive-edge trigger).
●ADDR=32h
DLYCNT01M (LED1 PWM Delay setting register–High 4bit-: Read/Write)
Bit 7 6 5 4 3 2 1 0
Register
Name
－
－ － －
DLY01[11] DLY01[10] DLY01[9] DLY01[8]
Default －
－ － － 0 0 0 0
This register is used to make setting of delay width for PWM light modulation in a total of 12 bits, i.e., Bit7-0 when
ADDR31h and Bit3-0 when ADDR32h.
DLY01[11：0] LED Delay Width
“0000 0000 0000” Normally set to Low (default)
“0000 0000 0001” HSYNC1 clock width
“0000 0000 0010” HSYNC 2 clock width
“0000 0000 0011” HSYNC 3 clock width
to to
“1111 1111 1100” HSYNC 4092 clock width
“1111 1111 1101” HSYNC 4093 clock width
“1111 1111 1110” HSYNC 4094 clock width
“1111 1111 1111” HSYNC 4095 clock width
The data in register is updated to the newest data when the next VSYNC signal rises up (positive-edge trigger).
●ADDR=33h～50h
This register is used to make PWM delay width setting for LED2 to LED16. The setting procedure is the same as that for
LED1 with ADDR set to 31h and 32h.
The data in register is updated to the newest data when the next VSYNC signal rises up (positive-edge trigger).