Datasheet
Datasheet
Datasheet
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BD9271KUT
TSZ02201-0F1F0C100260-1-2
© 2013 ROHM Co., Ltd. All rights reserved.
27.Feb.2015 Rev.004
www.rohm.com
TSZ22111・15・001
DAC output voltages to analog are converted with the decoders listed above.
0.3V: 0.3 / 5 * 4095 = 0F5h
0.4V: 0.4 / 5 * 4095 = 147h
0.5V: 0.5 / 5 * 4095 = 199h
0.6V: 0.6 / 5 * 4095 = 1EBh
0.8V: 0.8 / 5 * 4095 = 28Fh
1.0V: 1.0 / 5 * 4095 = 333h
1.2V: 1.2 / 5 * 4095 = 3E7h
1.5V: 1.5 / 5 * 4095 = 4CCh
The data in register EAMPREF is update to the newest data when the next VSYNC signal rises up (positive-edge
trigger).
●ADDR=0Fh
VSYNCREG (VSYNCREG control register: Read/Write)
Bit 7 6 5 4 3 2 1 0
Register
Name
-
- - - - - - VSNC_REG
Default
- - - - - - - 0
If VSYNC is not used, the register can be controlled by turning ON/OFF VSYNCREG instead of VSYNC.
The data in register is updated to the newest data immediately when the new data is written.
●ADDR=10h
SSMASKSET (Soft start mask register: Read/Write)
Bit 7 6 5 4 3 2 1 0
Register
Name
SSMASK[7] SSMASK[6] SSMASK[5] SSMASK[4] SSMASK[3] SSMASK[2] SSMASK[1] SSMASK[0]
Default
0 0 0 0 1 1 0 0
This register is used to make mask interval setting of abnormal protection (in sync with VSYNC) for the startup of power
supply.
This count starts up from VSYNC pulse input. The count value is not relation with the STB pin signal or the register LEDEN.
Please refer to the timing chart (soft start mask) in detail.
Decoder
SSMASK[7:0] SS mask interval
“0000 0000” No mask time
“0000 0001” VSYNC 2clks
“0000 0010” VSYNC 3clks
“0000 0011” VSYNC 4clks
- -
“1111 1101” VSYNC 254clks
“1111 1110” VSYNC 255clks
“1111 1111” VSYNC 256clks
The data in register is updated to the newest data when the next VSYNC (positive-edge trigger).
●ADDR=11h
DTYCNT01L (LED1 PWM duty setting register - Low 8 bits -: Read/Write)
Bit 7 6 5 4 3 2 1 0
Register
Name
DTY01[7] DTY01[6] DTY01[5] DTY01[4] DTY01[3] DTY01[2] DTY01[1] DTY01[0]
Default
0 0 0 0 0 0 0 0
The data in register is updated to the newest data when the next PWM signal rises up (positive-edge trigger).
●ADDR=12h
DTYCNT01M (LED1 PWM duty setting register - High 4 bits -: Read/Write)
Bit 7 6 5 4 3 2 1 0
Register
Name
－
－ － －
DTY01[11] DTY01[10] DTY01[9] DTY01[8]
Default －
－ － －
0 0 0 0
VSNC_REG VSYNCREG control
0 OFF
１ ON