User Manual

chapter 4:BIOS Setting
4.4 Advanced Chipset Features
DRAM Timing Selectable
Manual/By SPD.Select"By SPD" to allow BIOS to get the optimized timing data
from the data stored on the DIMM modules.Otherwise,select"Manual"to
configure the following timing constrains.
CAS Latency Time
Specifies the number of SCLKs between the time when the read command is
sampled by DRAM and the Whitney Sample reads data from DRAM.Available
setting are 1.5,2,2.5.
Active toPrecharge Delay
Specifies the active to precharge delay:The setting is 7,6,5.
DRAM RAS-to-CAS Delay
Specifies the length of the delay inserted between the RAS and CAS signals of
the DRAM system memory access cycle. The settings are 2 SCLKs or 3 SCLK
s. Default setting is "3".
DRAM RAS Precharge
Specifies the length of the RAS precharge part of the DRAM system memory
access. Available settings: 2 SCLKs, or 3 SCLKs. Default setting is "3".
DRAM DATA Integrity Mode
Display integrity mode of the DIMM modules.Option are Non-ECC/ECC.Defaults
setting is "Non-ECC".
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Mainboard Manual