User's Manual

Page 24 Mainboard User's Manual
SDRAM CAS Latency Time
Specifies the number of SCLKs between the time when the Read command
is sampled by SDRAM and the Whitney Sample reads data from SDRAM.
Available settings are 3(SCLKs) or 2. Default is "3".
DRAM Cycle Time Tras/Trc
Specifies the length of the SDRAM cycle time in SCLKs. Available options
are 7/9, and 5/7. Default is "7/9".
SDRAM RAS-to-CAS Delay
Specifies the length of the delay inserted between the RAS and CAS signals
of the SDRAM system memory access cycle. The settings are Auto, 2 SCLKs
or 3 SCLKs. Default setting is "3".
SDRAM RAS Precharge Time
Specifies the length of the RAS precharge part of the SDRAM system
memory access. Available settings: Auto, 2 SCLKs, or 3 SCLKs. Default
setting is "3".
System BIOS Cacheable
Enabled / Disabled System BIOS cache. Default setting is "Enabled".
Video BIOS Cacheable
Enabled / Disabled Video BIOS cache. Default setting is "Enabled".
Memory Hole At 15M-16M
Enabled / Disabled Memory Hole at 15M-16M. Default is "Disabled".
Advanced Chipset Features