User manual

10. Parallel I/O
94
76
5
4
32
10
00000
Port Port Port
21 0
Debounce
0 Disable
†
1 Enable
Register: Debounce Configure
Mode: Enhanced (Bank 2)
Address: 78h
Access: Read and Write
Debounce Configure Register
Note: This register controls whether each individual port or the external sense inputs
are passed through the debounce logic before being recognized.
76
5
4
32
10
00
Port Port Port
2
10
Port
2
Port
1
Port
0
Duration
00 4 µs
01 64 µs
10 1 ms
11 8 ms
Register: Debounce Duration
Mode: Enhanced (Bank 2)
Address: 79h
Access: Read and Write
Debounce Duration Register
Note: This register controls the duration required by each input signal before it is
recognized by each individual input. Default values are 00, setting a 4µm debounce
period.
76
5
4
32
10
000000
0
1
Register: Debounce Clock
Mode: Enhanced (Bank 2)
Address: 7Bh
Access: Write
Debounce Clock Register
†
On power up or reset, these bits are set to 0.