User manual

6. DMA Controller
68
DMA Interrupt Enable Register
The DMAIEN register is used to individually connect channel 0 and channel 1’s transfer
complete signal to the ICU’s DMAINT interrupt request input.
REGISTER:
ADDRESS:
AT ADDRESS:
ACCESS:
D7 D6 D5
D4
D3 D2
D1
D0
---
R/W
1= Connect channel 0 EOP signal to the ICU DMAINT input
0= Do not connect EOP to ICU
1= Connect channel 1 EOP signal to the ICU DMAINT input
0= Do not connect EOP to ICU
Reserved
DMAIEN
0F01Ch
DMA interrupt enable register
Reserved
11
DMA Interrupt Enable Register
DMA Interrupt Status Register
DMAIS indicates which source activated the DMA interrupt request signal (channel 0
transfer complete, channel 1 transfer complete, channel 0 chaining, or channel 1
chaining).
REGISTER:
ADDRESS:
AT ADDRESS:
ACCESS:
D7 D6 D5
D4
D3 D2
D1
D0
---
R/O
1= Indicates that new re
q
uestor and tar
g
et address and count
information should be written to channel 0. This bit is cleared when
new transfer information is written to the channel. Writin
g
to the most
si
g
nificant bit of the tar
g
et address clears this bit. Outside chainin
g
Reserved
DMAIS
0F019h
DMA interrupt status register
Reserved
00
Reserved
00
1= Indicates that new re
q
uestor and tar
g
et address and count
information should be written to channel 1. This bit is cleared when
new transfer information is written to the channel. Writin
g
to the most
si
g
nificant bit of the tar
g
et address clears this bit. Outside chainin
g
1= Channel 0 has completed a buffer transfer. This bit is set onl
y
if bit 0
of the interrupt enable re
g
ister is set. Clearin
g
bit 0 of the DMA status
re
g
ister clears this bit. In chainin
g
mode, this bit becomes a don't care.
1= Channel 1 has completed a buffer transfer. This bit is set onl
y
if bit 1
of the interrupt enable re
g
ister is set. Clearin
g
bit 1 of the DMA status
re
g
ister clears this bit. In chainin
g
mode, this bit becomes a don't care.
Reserved
mode, this bit becomes a don't care.
mode, this bit becomes a don't care.
DMA Interrupt Status Register