User manual

6. DMA Controller

DMA0TAR3 0F086h --- Channel 0 target address 24-25

DMA1TAR0 0F002h 0002h Channel 1 target address 0-7

DMA1TAR1 0F002h 0002h Channel 1 target address 8-15

DMA1TAR2 0F083h 0083h Channel 1 target address 16-23

DMA1TAR3 0F085h --- Channel 1 target address 24-25

DMA0BYC0 0F001h 0001h Channel 0 byte count 0-7

DMA0BYC1 0F001h 0001h Channel 0 byte count 8-15

DMA0BYC2 0F098h --- Channel 0 byte count 16-23

DMA1BYC0 0F003h 0003h Channel 1 byte count 0-7

DMA1BYC1 0F003h 0003h Channel 1 byte count 8-15

DMA1BYC2 0F099h --- Channel 1 byte count 16-23

DMASTS 0F008h 0008h DMA status register

DMACMD1 0F008h 0008h DMA command register 1

DMACMD2 0F01Ah --- DMA command register 2

DMAMOD1 0F00Bh 000Bh DMA mode register 1

DMAMOD2 0F01Bh --- DMA mode register 2

DMASRR 0F009h 0009h DMA software request register

DMAMSK 0F00Ah 000Ah DMA single channel mask register

DMAGRPMSK 0F00Fh 000Fh DMA group channel mask

DMABSR 0F018h --- DMA bus size register

DMACHR 0F019h --- DMA chaining register

DMAIEN 0F01Ch --- DMA interrupt enable register

DMAIS 0F019h --- DMA interrupt status register

DMAOVFE 0F01Dh --- DMA overflow enable register

Pin Mux Configuration

The PINCFG register is used to connect /EOP and /DACK1 to the package pins.