User manual

6. DMA Controller
50
386 EX DMA CONTROLLER REGISTERS
The "386 EX DMA Controller Registers" table below lists the registers associated with
the DMA controller.
The following sections provide bit-level definitions for all registers associated with the
DMA controller. Bit definitions in this section assume intended use of one or more DMA
channels. Note that the reset state, if defined, is the hardware reset state.
The reset state bit definitions include:
0 is a bit that is set to a logical 0 by a hardware reset.
1 is a bit that is set to a logical 1 by a hardware reset.
--- is a bit that is reserved, write a ‘0’ to these bits.
ND is a bit whose reset state is not defined after a hardware reset.
Any bit described as ‘Reserved’ should be written with a 0 (unless otherwise indicated.)
386 EX DMA Controller Registers
Re
g
ister Address Ex
p
anded Address PC/AT Descri
p
tion
PINCFG 0F826h --- Pin mux configuration
DMACFG 0F830h --- Peripheral connections and mask
DMA0REQ0 0F010h --- Channel 0 requestor address 0-7
DMA0REQ1 0F010h --- Channel 0 requestor address 8-15
DMA0REQ2 0F011h --- Channel 0 requestor address 16-23
DMA0REQ3 0F011h --- Channel 0 requestor address 24-25
DMA1REQ0 0F012h --- Channel 1 requestor address 0-7
DMA1REQ1 0F012h --- Channel 1 requestor address 8-15
DMA1REQ2 0F013h --- Channel 1 requestor address 16-23
DMA1REQ3 0F013h --- Channel 1 requestor address 24-25
386 EX DMA Controller Registers table (continued)
DMA0TAR0 0F000h 0000h Channel 0 target address 0-7
DMA0TAR1 0F000h 0000h Channel 0 target address 8-15
DMA0TAR2 0F087h 0087h Channel 0 target address 16-23