ZT 8903 ZT 8904 ZT 89CT04 Single Board 386 EX Computer Hardware User Manual
CONTENTS MANUAL ORGANIZATION .....................................................................................................................6 1. INTRODUCTION .................................................................................................................................8 PRODUCT DEFINITION .............................................................................................................8 ZT 8904................................................................................
Contents 4. INTERRUPT CONTROLLER .............................................................................................................31 PROGRAMMABLE REGISTERS...............................................................................................31 INTERRUPT ARCHITECTURE INITIALIZATION REGISTERS (ICW1-ICW4)................34 OPERATIONAL REGISTERS (OCW1-OCW3)..............................................................36 STATUS REGISTERS (IRR, ISR, IPR) ......................................
Contents PROGRAMMABLE REGISTERS...............................................................................................78 BAUD RATE DIVISORS ...............................................................................................78 DIVISOR LATCH LSB AND MSB..................................................................................79 INTERRUPT CONTROL REGISTER ............................................................................80 INTERRUPT STATUS REGISTER.........................
Contents CONNECTOR DESCRIPTIONS .................................................................................123 CABLES .....................................................................................................................133 C. PIA SYSTEM SETUP CONSIDERATIONS .....................................................................................139 PREVENTING SYSTEM LATCHUP ........................................................................................
MANUAL ORGANIZATION The ZT 8904 family of products includes the ZT 8904, ZT 89CT04, and ZT 8903 products. The ZT 8904 is a highly integrated 386 EX single board computer which can be operated as a stand alone, as a single master in an STD 32 architecture, or as a permanent or temporary master in an STD 32 architecture. All features of the ZT 8903 and ZT 8904 are the same, except that the ZT 8903 includes fewer features.
Manual Organization Chapter 11, "System Registers", discusses the three system registers used to control and monitor a variety of functions on the ZT 8904. Chapter 12, "Watchdog Timer", lists the major features of the watchdog timer which monitors the ZT 8904 operation and takes corrective action if the system fails to function as programmed. Chapter 13, "Local BUS Video", includes information on the local bus interface which permits high speed peripherals direct access to the CPU bus.
1. INTRODUCTION This chapter provides a brief introduction to the ZT 8904. It includes a product definition, a list of product features, a functional block diagram, a description of each block, and a diagram locating the major components of the board. Unpacking information and installation instructions are included in Chapter 2, "Getting Started.
1. Introduction ZT 8904 The ZT 8904 is a highly integrated 386 EX single board computer. The board meets the needs of a wide range of industrial control and processing applications by operating stand alone, as a single master in an STD 32 architecture, or as a permanent or temporary master in an STD 32 architecture. ZT 89CT04 The ZT 89CT04 extends the ZT 8904 operating temperature range from 0 to 65º C to -40º to +85º C.
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1. Introduction DEVELOPMENT CONSIDERATIONS Ziatech offers a variety of software options for ZT 8904 applications. These options include STD ROM, STAR BIOS, and Ziatech's Industrial BIOS. Contact the Ziatech for additional options. STD ROM allows programmers to develop ROM-based applications without the use of an operating system. STD ROM connects the ZT 8904 to an IBM-compatible personal computer through a high speed serial link.
1. Introduction 386 EX CPU ZT 8904 The ZT 8904 supports the Intel 386 EX CPU operating at 25 MHz. The 386 EX is a fully static 32-bit CPU core integrated with standard PC peripherals. Integrated peripherals include serial controller, interrupt controller, DMA controller, counter/timers, and watchdog timer. The 386 EX supports a 64 Mbyte memory address space and a 64 Kbyte I/O address space.
1. Introduction Memory and I/O Addressing The ZT 8904 includes 1 Mbyte of system RAM, 1, 2, or 4 Mbytes of Flash, and 128 Kbytes of battery-backed RAM. The battery-backed RAM is not available on the ZT 8903. System RAM can be expanded from 1 Mbyte to 5 Mbytes with the addition of an optional memory module. Memory operations up to 16 Mbytes that are not decoded by local memory devices are directed to the STD bus.
1. Introduction The serial ports are configured as DTE and are available through the J1 80-pin frontplane connector. Optional cables convert the serial port interface to standard 9-pin D-shell connectors. The ZT 90200 cable provides the serial interface for the ZT 8904 and ZT 89CT04. The ZT 90203 cable provides the serial interface for the ZT 8903. A null-modem option is required to convert the DTE configuration to DCE. See Chapter 8, "Serial Controller" for more information.
1. Introduction Timers Three timers are included on the ZT 8904. Operating modes supported by the timers include interrupt on count, frequency divider, square wave generator, software triggered, hardware triggered, and one shot. The number of counter/timers available to the application programmer depends on the operating system. For example, the Ziatech MS DOS operating system uses timer 0 to generate system tick and timer 2 to control the speaker. Timer 1 is available to the application.
1. Introduction Keyboard Controller The ZT 8904 includes a PC/AT® keyboard controller that operates when the zVID local bus video adapter is installed. The keyboard connector is located on the zVID adapter. AC Power-Fail Protection With the addition of an AC transformer (connected to connector J3), the ZT 8904 monitors AC power to permit an orderly shutdown during a power failure.
2. GETTING STARTED This chapter summarizes the information needed to make the ZT 8904 operational. Read this chapter before attempting to use the board. UNPACKING Please check the shipping carton for damage. If the shipping carton and contents are damaged, notify the carrier and Ziatech for an insurance settlement. Retain the shipping carton and packing material for inspection by the carrier. Save the anti-static bag for storing or returning the ZT 8904.
2. Getting Started • Local RAM Drive - 8-bit battery-backed RAM (not available on the ZT 8903) paged for 128 Kbytes • System BIOS - 16-bit pseudo static RAM shadowed from Flash #0 • Extended RAM - Optional 16-bit pseudo static RAM module • Flash #0 - 8-bit Flash • Flash #1 - Optional 8-bit Flash • STD bus Expansion - 8-bit or 16-bit expansion memory • Reserved - Not available STD bus expansion memory is transferred at a rate of up to 1 Mbyte/second for 8-bit data and 1.
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2. Getting Started J2 (FRONTPLANE INTERRUPT) J5 (MEMORY EXPANSION) J3 (AC POWER FAIL) J3 J7 (POWER CONNECTOR) J2 J5 J4 J1 P/E (STD 32 INTERFACE) J6 J6 (LOCAL BUS) J4 (PARALLEL I/O) J1 (SERIAL/PRINTER I/O) Connector Locations JUMPER DESCRIPTIONS The ZT 8904 includes several jumper options that tailor the operation of the board to specific application requirements. These options are summarized in Appendix A, "Jumper Configurations.
2. Getting Started The ZT 8904 is configured during the boot sequence by the BIOS. The BIOS uses system configuration information stored as SETUP parameters. To access the SETUP utility, either boot the system and press the "S" key during the system RAM check, or run the SETUP.COM utility from the MS-DOS prompt. The SETUP parameters are saved in the battery-backed RAM portion of the ZT 8904's real-time clock device. The SETUP parameters can also be saved in a file format, or as the programmed BIOS defaults.
3. STD BUS INTERFACE The ZT 8904 includes several I/O devices common to industrial control applications. The ZT 8904 also operates with the STD 32 bus architectures to support additional I/O and memory mapped devices as required by the application. This section discusses the STD 32 architecture and its effect on the operation of the ZT 8904.
3. STD Bus Interface STD 32 BUS COMPATIBILITY The ZT 8904 is compatible with Revision 1.2 of the STD 32 Bus Specification (Ziatech part number ZT MSTD32). Optional STD 32 features are discussed in terms of compliance levels. • Permanent Master: SA16, SA8 - I, SDMABP, {MD} • Temporary Master: SA16, SA8 - I, SDMABP, {MD} Compliance Levels The following is a brief description of the STD 32 compliance levels supported by the ZT 8904.
3. STD Bus Interface Maskable Interrupts The STD bus maskable interrupts monitored by the ZT 8904 are INTRQ* (P44), INTRQ1* (P37), INTRQ2* (P50), INTRQ3* (E67), and INTRQ4* (P5). These maskable interrupts are routed to a jumper configuration block (W17-22) for added flexibility. Note that an STD 32 backplane is needed to use INTRQ3*. The ZT 8904 is also capable of generating STD bus interrupts. This feature is useful in multiple master systems to coordinate communications between processors.
3. STD Bus Interface In an edge-triggered architecture, multiple interrupt sources should not share the same interrupt request signal because it is possible to miss an interrupt request from one source while an interrupt request from another source is being serviced. For this architecture, each interrupt source requires a unique connection to the interrupt controller, as shown in the "STD Bus Vectored Interrupt Structure" figure following.
3. STD Bus Interface RESET The ZT 8904 is automatically reset with a precision voltage monitoring circuit that detects when Vcc is below the acceptable operating limit of 4.75 V. Other sources of reset include watchdog timer stage 2, local pushbutton switch, and the STD bus pushbutton reset signal, PBRESET* (P48). The ZT 8904 responds to any of these reset sources by initializing local peripherals and driving the STD bus system reset, SYSRESET* (P47).
3. STD Bus Interface 904 00 ZT2 ZT 8 P MASORARY TEM TE P MASORARY R TEM TER P MASORARY PER T ER MA ZT 8 ZT 8 MEM I/O SLA VE ORY SLA 904 T VE EM ZT 8 904 904 N MA STEENT SL R ARBOT X ITE R ded bed r Em pute Com TM Multiple Master Architecture Intelligent I/O An intelligent I/O system includes a single ZT 8904 and one or more intelligent I/O boards, such as the ZT 8832. This architecture is illustrated in the following figure "Intelligent I/O Architecture.
3. STD Bus Interface ZT 8 832 INTEL 832 INTE 00 ZT2 ZT ded bed r Em pute Com LLIG ENT LLIG I/O I/O ENT LIG I/O ENT 832 INTE ZT 8 ZT 8 MEM I/O SLA ORY VE SLA 832 IN VE TE ZT 8 LLIG I/O ENT 890 4 TM Intelligent I/O Architecture Multiple Master Vs. Intelligent I/O Both multiple master and intelligent I/O architectures are excellent methods of increasing system performance.
3. STD Bus Interface • An STD 32 backplane is required. The STD-80 backplane does not support the bus exchange protocol (DREQx* and DAKx*). • A ZT 89CT39, or equivalent bus arbiter, is needed to manage ZT 8904 access to the STD bus resources. The arbitration may also be built directly on to the permanent master if a ZT 8904 is not used for this function.
4. INTERRUPT CONTROLLER The ZT 8904 includes two Intel-compatible 8259 cascaded interrupt controllers that provide a programmable interface between interrupt-generating peripherals and the CPU. The interrupt controllers monitor 15 interrupts with programmable priority. When peripherals request service, the interrupt controller interrupts the CPU with a pointer to a service routine for the highest priority device. The major features of the interrupt architecture are listed below.
4. Interrupt Controller following table. The base address of the master interrupt controller is 20h and the base address of the slave interrupt controller is A0h.
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4. Interrupt Controller Interrupt Architecture Initialization Registers (ICW1-ICW4) Each interrupt controller must be initialized before it is used. Initialization consists of writing two, three, or four initialization commands. The programming sequence for these registers is given in the "Interrupt Initialization Programming" figure below. ICW1, ICW2, and ICW3 must be programmed during each initialization sequence. ICW4 may or may not be programmed, as required by the application.
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4. Interrupt Controller Operational Registers (OCW1-OCW3) The operation of each interrupt controller is managed by three 8-bit operational registers. These registers are programmed in any sequence for things such as enabling and disabling interrupt requests and changing interrupt priorities.
4. Interrupt Controller 7 5 6 4 3 2 0 1 P 1 0 Register: OCW3 SMM 0 SLCT Address: Base + 0 Access: Write Read Register 00 Do not use 01 Do not use 10 Select IR register 11 Select IS register Poll Command 0 No poll 1 Poll Mask Selection 00 Do not use 01 Do not use 10 Standard mask 11 Special mask Operational Register OCW3 Status Registers (IRR, ISR, IPR) Each interrupt controller includes three status registers. A status register is selected by programming the first three bits of OCW3.
4. Interrupt Controller 7 6 5 4 3 IR 0 0 0 0 2 1 0 Active Register: IPR Address: Base + 0 Access: Read Highest Active Request 000 IR0 001 IR1 010 IR2 011 IR3 100 IR4 101 IR5 110 IR6 111 IR7 Interrupt 0 No Interrupt present 1 Interrupt present Status Register IPR ADDITIONAL INFORMATION Refer to the Ziatech Industrial Computer System Manual for more information on the operating system's use of the interrupt inputs.
5. COUNTER/TIMERS The ZT 8904 includes one Intel-compatible 8254 device with a total of three programmable counter/timers. The counter/timers are useful for software timing loops, timed interrupts, and periodic interrupts. The major features of the counter/timers are listed below. • Three 16-bit counter/timers • Six programmable operating modes • Binary and BCD counting • Interrupt and polled operation The counter/timer architecture is illustrated in the "Counter/Timer Architecture" figure below.
5. Counter/Timers The six programmable operating modes are summarized in the "Counter/Timer Operating Modes" table following.
5. Counter/Timers PROGRAMMABLE REGISTERS The counter/timers are accessed through four I/O addresses as shown in the following table. Each counter/timer occupies an I/O port address through which the preset count values are written and both the count and status information is read. The Control register occupies the remaining I/O port address, which services all three counter/timers.
5. Counter/Timers Status Register Each counter/timer has a Status register. The Status register must be read using the multiple latch command specified in the Control register.
5. Counter/Timers Control Register The Control register is used to initialize the counter/timers and to select the method of reading the count and status information. The Control register is best described by dividing it into three formats as illustrated below.
5. Counter/Timers 7 6 1 1 5 4 3 2 1 CTL STL CT2 CT1 CT0 0 0 Register: Multiple Latch Control Address: 43h Access: Write Counter Selection 001 Counter 0 010 Counter 1 100 Counter 2 Status Latch 0 Enabled 1 Disabled Control Latch 0 Enabled 1 Disabled Multiple Latch Control Register ADDITIONAL INFORMATION Refer to the Ziatech Industrial Computer System Manual for more information on the operating system's use of the counter/timers.
6. DMA CONTROLLER The DMA controller used on the ZT 8904 is contained within the 386 EX microprocessor. It improves system operation by allowing external or internal peripherals to directly transfer data to or from ZT 8904 memory. The DMA controller can transfer data between memory and I/O with 8-bit or 16-bit data path widths. It has features that are not available on an 8237A, and it can be configured to operate in an 8237A-compatible mode.
6. DMA Controller connections internal to the 386 EX. Note that the synchronous serial channel is not implemented on the ZT 8904 in favor of providing an additional asynchronous serial channel. Channel 0 supports the following devices as DRQ sources (DMACFG.6-4). • External DMA slave request • COM1 receive buffer full • COM2 transmit buffer empty • Timer/Counter unit 1 OUT1 Channel 1 supports the following devices as DRQ sources (DMACFG.2-0).
6. DMA Controller DMA IMPLEMENTATION The ZT 8904 DMA architecture external to the 386 EX is illustrated in the following figure, "DMA Architecture." The ZT 8904 supports a single DMA channel for STD bus DMA slaves. STD bus DMA slaves are I/O devices that use the ZT 8904 DMA channel 0 to transfer data between backplane I/O and ZT 8904 local memory. The ZT 8904 supports the use of both DMA channels for specific 386 EX internal peripherals.
6. DMA Controller 16 EOP R84 1 VCC U18C 2 RESSM-04751 4 1 W24 JPRX3 ICPSMCI-74FCT540Q BUSRQ* / BRQ_DST 1 U43 4 U18B 3 17 1 W25 JPRX3 2 ICPSMCI-7S32F 3 2 113 117 2 ICPSMCI-74FCT540Q 128 / BUSAK 3 LPT_DRQ 1 R80 2 VCC RESSM-04751 / LPT_DAK 3 W26 JPRX3 2 W27 JPRX3 EOP/CT51 3 1 118 112 DRQ0/DCD1 DAK0/CS5 DRQ1/RXD1 DAK1/TXD1 1 2 ICP5MCI-386EX CT51 DCD1 RXD1 TXD1 DMA Architecture DMA TRANSFER CYCLES The ZT 8904 supports DMA channel 0 as a channel for backplane DMA slaves.
6. DMA Controller An external device or an internal peripheral requests service by activating a channel’s request input (DRQn). A requester in memory requests service through the DMA software request register. The requester either transfers data to or retrieves data from the target. Programming a DMA Channel A channel is programmed by writing to a set of registers including requester address, target address, byte count, and control registers.
6. DMA Controller 386 EX DMA CONTROLLER REGISTERS The "386 EX DMA Controller Registers" table below lists the registers associated with the DMA controller. The following sections provide bit-level definitions for all registers associated with the DMA controller. Bit definitions in this section assume intended use of one or more DMA channels. Note that the reset state, if defined, is the hardware reset state.
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6. DMA Controller Peripheral Connections and Mask The DMACFG register is used to select of the hardware DRQ sources for each channel and to mask the /DACKn signals at their pins when using internal requesters.
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6. DMA Controller D7 D6 D5 D4 D3 ND ND ND ND ND D2 D1 D0 ND ND ND REGISTER: DMA1BYC2 Channel 1 byte count bits 16-23 ADDRESS: 0F099h AT ADDRESS: --ACCESS: R/W Channel 1 byte count bit 16 Channel 1 byte count bit 17 Channel 1 byte count bit 18 Channel 1 byte count bit 19 Channel 1 byte count bit 20 Channel 1 byte count bit 21 Channel 1 byte count bit 22 Channel 1 byte count bit 23 Channel 1 Byte Count Bits 16-23 DMA Status Register The DMASTS register is used to check channel status individually.
6. DMA Controller DMA Command Registers The DMACMD1 resister is used to enable both channels and to select the rotating method for changing the bus priority control structure. Under all prioritization schemes, the DRAM refresh control unit receives highest priority.
6. DMA Controller DMA Mode Registers The DMAMOD 1 register is used to select a particular channel's data-transfer mode and transfer direction, and to enable the channel's auto-initialize buffer-transfer mode. You can configure the DMA controller to modify the target address during a buffer transfer by clearing DMAMOD2.2, then use DMAMOD1.3 to specify how the channel modifies the address.
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6. DMA Controller DMA Single Channel Mask Register Use the DMAMSK register to enable or disable hardware requests for one channel at a time.
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6. DMA Controller DMA Interrupt Enable Register The DMAIEN register is used to individually connect channel 0 and channel 1’s transfer complete signal to the ICU’s DMAINT interrupt request input.
6. DMA Controller DMA Overflow Enable Register Use DMAOVFE to specify whether all 26 bits or only the lower 16 bits of the target and requestor addresses are incremented or decremented during buffer transfers and whether all 24 bits of the byte count or only the lower 16 bits of the byte count are incremented or decremented during buffer transfers. A byte count configured for 16-bit decrementing expires when it is decremented from 0000h to FFFFh.
7. REAL-TIME CLOCK The ZT 8904 includes one Motorola®-compatible 146818 real-time clock. The real-time clock provides clock and 100-year calendar information in addition to 242 bytes of CMOS setup static RAM. These functions are battery backed for continuous operation even in the absence of system power. The RAM is used by the operating system BIOS to store configuration information. The major features of the real-time clock are listed below.
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7. Real-Time Clock Register A 7 6 5 4 UIP 0 1 0 3 2 1 Interrupt Rate 0 Register: A Address: Offset+0Ah Access: Read and Write Rate Selection 0000 No Interrupts 0001 3.90625 ms 0010 7.8125 ms 0011 122.070 us 0100 244.141 us 0101 488.281 us 0110 976.562 us 0111 1.953125 ms 1000 3.90625 ms 1001 7.8125 ms 1010 15.625 ms 1011 31.25 ms 1100 62.
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7. Real-Time Clock Register D 7 6 5 4 3 2 1 0 VRT 0 0 0 0 0 0 0 Register: D Address: Offset+0Dh Access: Read Valid RAM 0 Invalid 1 Valid Register D ADDITIONAL INFORMATION Refer to the National Semiconductor PC87306 datasheet for more information on the real-time clock operating modes. The product folder for the PC87306, including the data sheet, is available on the web site http://www.national.com/pf/PC/PC87306.html.
8. SERIAL CONTROLLER This chapter discusses operation of the four ZT 8904 serial ports. It provides descriptions of the two software-configurable serial port registers included on the ZT 8904. ZT 8904 SPECIFICS The ZT 8904 includes four serial ports: two serial ports (COM1 and COM2) compatible with the 16450/8250, and two serial ports (COM3 and COM4) compatible with the 16550. The ZT 8903 includes only two serial ports, COM1 and COM2.
8. Serial Controller Address Mapping The address mapping for the PC standard architecture and the ZT 8904 is shown below. Serial Channel PC Port Address ZT 8904 Port Address COM1 3F8-3FF 3F8-3FF COM2 2F8-2FF 2F8-2FF COM3 3E8-3EF 2E0-2E7 COM4 2E8-2EF 2E8-2EF Interrupt Selection The interrupt mapping for the PC standard architecture and the ZT 8904 is shown below. Different interrupt levels for COM3 and COM4 interrupts are selectable through the interrupt jumper block.
8. Serial Controller RS-485 Operation Two of the serial channels, COM1 and COM2, are software programmable for RS-232 or RS-485 operation. The RS-485 functionality is not available on the ZT 8903. The software selection is made through bits 2 and 3 of System Register 2. The RS-485 architecture is shown below.
8. Serial Controller PROGRAMMABLE REGISTERS Six registers are available for initializing and controlling each serial channel. The following table "Serial Controller Register Addressing" shows the I/O port addressing for the COM1 registers. The remaining serial channels are located as follows: COM2: 2F8-2FFh COM3: 2E0-2E7h COM4: 2E8-2EFh The topics that follow illustrate the 16-bit divisor latch, baud rate divisors, and the six programmable registers for each serial channel.
8. Serial Controller Baud Rate Divisors Baud Rate Divisor (dec/hex) Percent Error 50 2304/1440h 0 75 1536/960h 0 150 768/480h 0 300 384/240h 0 600 192/120h 0 1200 96/60h 0 1800 64/40h 0 2000 58/3Ah 0.69 2400 48/30h 0 3600 32/20h 0 4800 24/18h 0 7200 16/10h 0 9600 12/Ch 0 19200 6/6h 0 38400 3/3h 0 56000 2/2h 2.
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8. Serial Controller Line Control Register 7 6 5 4 3 2 DIV BRK PTS PTE PEN STP 1 0 Length Register: Line Control Address: 3FBh Access: Read and Write Character Length 00 5 bits 01 6 bits 10 7 bits 11 8 bits Stop Bits 0 1 bit 1 2.0 bits for Length = 6,7, or 8 1.
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9. CENTRONICS PRINTER INTERFACE The bidirectional printer interface fully supports a Centronics-compatible printer. The Centronics interface is available through the J1 connector. Refer to the table "J1 Peripheral Pinout" in Appendix B for the connector pin assignments. PROGRAMMABLE REGISTERS The following topics illustrate the programmable registers for the Centronics printer interface.
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10. PARALLEL I/O The ZT 8904 includes six 8-bit parallel ports for a total of 48 I/O signals. Three of the parallel ports are available to the application through frontplane connector J4. The remaining three parallel ports are dedicated to controlling and monitoring local operations. The general operation of the six parallel ports is explained in this chapter. The specific features managed by the dedicated ports are explained in Chapter 11, "System Registers.
10. Parallel I/O Passive Termination Internal Data Bus Connector J4 Output Data Latch Output Buffer Event Detect Logic Debounce Logic Input Buffer Parallel Port Functional Diagram Output Latch The output latch stores the data present on the internal data bus during a write operation to the parallel port. The data is latched until altered by another parallel port write, until a system reset, or until the power is turned off.
10. Parallel I/O Input Buffer The input buffer is enabled during read operations to transfer the data from connector J4 to the internal data bus. If the parallel port bit is configured as input, the data read is the data driven by an external device. The input buffer is an inverting device. This means that data read from the parallel port as a logical 0 is a TTL high at connector J4, and data read from the parallel port as a logical 1 is a TTL low at connector J4.
10. Parallel I/O 16C50A Enhanced Operating Mode Enhanced operation adds extended event sense and input debounce capabilities. It is selected with four consecutive writes of 07h, 0Dh, 06h, and 12h to I/O port address 7Dh immediately after a power cycle or a reset. Three enhanced register banks are selected by programming bits 6 and 7 of I/O port 7Fh with a 00 for bank 0, a 01 for bank 1, and a 10 for bank 2. Ziatech Industrial Computer Systems software configures the 16C50A for enhanced operation.
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10. Parallel I/O 7 6 5 Bank Bank 0 1 0 4 0 3 2 1 0 Port Port Port 2 1 0 0 Register: Write Inhibit/Bank Address Mode: Enhanced (Bank 0) Address: 7Fh Access: Read and Write Port Write Inhibit 0 Inactive 1 Active Bank Address 00 Bank 0 01 Bank 1 10 Bank 2 11 Undefined Write Inhibit /Bank Address Register Note: A 11b is an invalid state and should never be written to the Mask Register.
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10. Parallel I/O 7 0 4 5 6 0 0 3 0 2 1 0 Port Port Port 2 1 0 0 Register: Debounce Configure Mode: Enhanced (Bank 2) Address: 78h Access: Read and Write Debounce 0 Disable† 1 Enable Debounce Configure Register Note: This register controls whether each individual port or the external sense inputs are passed through the debounce logic before being recognized.
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11. SYSTEM REGISTERS Three system registers are used to control and monitor a variety of functions on the ZT 8904. These registers are implemented with the same Ziatech 16C50A ASIC that implements the 24 parallel I/O lines discussed in "Parallel I/O," Chapter 10. The 16C50A operating instructions are outlined below. Refer to "Parallel I/O" for a complete discussion. • The reset state for all bits is a logical 0.
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11. System Registers 7 6 5 4 3 2 1 0 System Register 2 LED BDS VPP VMX C2S C1S KBD MIR Multiprocessing Interrupt 0 Active 1 Inactive Keyboard Interrupt 0 Local 1 System Com 1 Interface 0 RS 485 1 RS 232 Com 2 Interface 0 RS 485 1 RS 232 Video Mux 0 Enable 1 Disable VPP Generator 0 Enable 1 Disable Bus Request Destination 0 Enable 1 Disable Light Emitting Diode 0 Enable 1 Disable System Register 2 ADDITIONAL INFORMATION See Chapter 10, "Parallel I/O," for additional details.
12. WATCHDOG TIMER The primary function of the watchdog timer is to monitor ZT 8904 operation and take corrective action if the system fails to function as programmed. The major features of the watchdog timer are listed below. • Single-stage or two-stage operation • Enabled and disabled through software control • Armed and strobed through software control WATCHDOG TIMER OPERATION The watchdog timer architecture is illustrated in the "Watchdog Timer Architecture" figure.
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12. Watchdog Timer Watchdog Timer Clear Register The Watchdog Timer Clear register is programmed with a lockout sequence to enable watchdog timer mode and to reload the counter. The lockout sequence is shown below. • Word write of F01Eh to F4C8h • Word write of 0FE1h to F4C8h 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - Register: Watchdog Clear Address: F4C8h Access: Write Only Word Write Sequence 1. F01Eh 2.
12. Watchdog Timer Watchdog Timer Counter Registers The Watchdog Timer Counter registers hold the current value of the down counter. Application software reads these registers to determine the current count value. A reload operation automatically transfers the contents of the Watchdog Reload registers to the Watchdog Timer registers.
12. Watchdog Timer Watchdog Timer Reload Registers The Watchdog Timer Reload registers are programmed with two word operations to set the reload value. After a lockout sequence, these registers are write protected until after the next reset or power cycle. A reload operation automatically transfers the contents of the Watchdog Reload registers to the Watchdog Timer registers.
13. LOCAL BUS VIDEO The ZT 8904 includes a local bus interface to permit high speed peripherals direct access to the CPU bus. This bus operates synchronously at CPU speeds of 25 MHz. Ziatech offers zVID video adapters designed specifically for this local bus interface. These adapters give superior performance over STD bus video solutions by running with four times the data width and more than four times the operating frequency. Major features of the video adapters are listed below.
14. NUMERIC DATA PROCESSOR The ZT 8904 includes a socket at location U26 designed to accept an 80387 numeric data processor. The numeric data processor extends the CPU instruction set to include trigonometric, logarithmic, and exponential functions. Adding a numeric data processor increases the application performance by as much as 10% on Whetstone and Livermore benchmarks. The numeric data processors qualified to work in the ZT 8904 are listed below.
15. PROGRAMMABLE LED The ZT 8904 includes two Light-Emitting Diodes (LEDs) located immediately below the board extractor. The green LED is for the optional IDE disk drive; the red LED is general purpose. The red LED is software programmable through the LED bit in System Register 2. Writing a logical 0 to the LED bit turns the LED off and writing a logical 1 to the LED bit turns the LED on. The LED is turned off after a power cycle or a reset.
15. Programmable LED ;------------------------------------------------------------; led_off turns off the led.
16. AC POWER FAIL The ZT 8904 supports AC power-fail detection as a means for giving the application advanced warning of an impending power failure. The advanced warning may be used by the application for performing operations such as saving critical data and entering a dormant state. The ZT 8904 requires a transformer-isolated AC voltage of no more than 30 V from the same source that provides the system power. Ziatech's optional AC wall transformer (ZT 90071) meets these requirements.
A. JUMPER CONFIGURATIONS The ZT 8904 includes several options that tailor the operation of the board to requirements of specific applications. Options are made by installing and removing shorting receptacles (jumpers). JUMPER OPTIONS The ZT 8904 includes jumpers with two posts and jumpers with three posts. Jumpers having only two posts are labeled Wx, where x defines the jumper number (for example, W12). Jumpers having three posts are labeled Wx "a" and "b" (for example, W16a and W16b).
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A. Jumper Configurations Jumper Descriptions The following topics list the jumpers in numerical order and provide a detailed † description of each jumper. A dagger ( ) indicates the default jumper configuration. W1-7 Reserved for Ziatech use. Do not install these jumpers. W8 Numeric Coprocessor - indicates the presence of a numeric coprocessor.
A. Jumper Configurations W12-15 RS-485 Duplex Selection - independently selects half duplex or full duplex for each RS485 channel. The COM1 and COM2 serial ports are software configured for RS-232 or RS-485 operation through System Register 2. If configured for RS-485, the following jumpers adjust the RS-485 architecture to a specific application. These jumpers do not apply to the ZT 8903.
A. Jumper Configurations W17-22 Maskable Interrupts - assigns up to nine interrupt sources to the interrupt controller inputs. Each interrupt input has two possible sources selected by installing a jumper in position "a" or position "b." Other combinations are possible with wire wrap techniques. Interrupt inputs not used in the application must be masked in software.
A. Jumper Configurations W24-27 CPU Configuration - connects external hardware functions to multiplexed CPU pins. The CPU multiplexes DMA channel 0 and DMA channel 1 with serial port COM2 signals. In short, if DMA channel 0 is used to support STD bus DMA (such as the Ziatech ZT 8954 floppy disk controller), Data Carrier Detect and Clear To Send are not available for COM2.
A. Jumper Configurations W28-31 RS-485 Transmitter Configuration - independently configures the transmitter input source and transmitter enable for the RS-485 channels. The COM1 and COM2 serial ports are software configured for RS-232 or RS-485 operation through System Register 2. If configured for RS-485, the following jumpers adjust the RS-485 architecture to a specific application. These jumpers do not apply to the ZT 8903.
B. SPECIFICATIONS This appendix describes the electrical, environmental, and mechanical specifications of the ZT 8904. It also includes illustrations of the board dimensions, the P/E connector pinouts, and cables commonly used with the ZT 8904, as well as tables showing the pin assignments for the ZT 8904's 10 connectors.
B. Specifications Battery Backup Characteristics Battery Voltage: 3V Battery Capacity: 255 mAH Real-time clock requirements: 5 µA maximum (when Vcc is below acceptable operating limits) Real-time clock data retention: 5 years minimum, 10 years typical Electrochemical Construction: Poly-carbonmonofluoride STD-80 Compatibility The ZT 8904 is designed for use in an STD 32 backplane environment.
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B. Specifications MECHANICAL SPECIFICATIONS The following topics list mechanical specifications, including card dimensions and weight, connectors, and cables. Card Dimensions and Weight The ZT 8904 meets the STD-80 Series Bus Specification for all mechanical parameters. In a card cage with 0.625 inch spacing, the ZT 8904 requires one card slot with or without the zVID local bus video adapter installed. Mechanical dimensions are shown in the "Board Dimensions" figure following and are outlined below.
B. Specifications Connectors The ZT 8904 includes 9 connectors to interface to the STD bus and application specific devices. Connector positions are illustrated in the "Connector Locations" figure below. A description and pin map for each connector is given in the following topics.
B. Specifications Viking S3VT68/5DE12 or equivalent for the card extender. The figure below, "P/E Connector Pinout," shows pin assignments for the E connector and the table "STD Bus Signal Loading, E Connector" shows signal assignments.
B. Specifications Connector Descriptions Connector Function J1 Peripheral J2 Frontplane Interrupt J3 AC Power Fail J4 Parallel I/O J5 Memory Expansion J6 Local Bus J7 Auxiliary Power J8 Optional IDE J9 Reserved J1 (Peripheral) J1 is a latching 80-pin (dual 40-pin) male transition connector with 0.05 inch contact spacing. The serial ports, 1284 parallel port, and an external battery connection are available through J1.
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B. Specifications J2 (Frontplane Interrupt) J2 is a latching 10-pin (dual 5-pin) male transition connector with 0.1 inch contact spacing. Frontplane interrupts are available through this connector. The pin assignments are given in the “J2 Frontplane Interrupt Pinout” table below. The mating connector is a T&B Ansley #622-1030 or equivalent.
B. Specifications J3 (AC Power Fail) J3 is a latching 2-pin male low-profile header with 0.1 inch contact spacing. The AC input signals for the optional power-fail detection feature are available through this connector. The pin assignments are given in the “J3 AC Power Fail Pinout” table following. The mating connector is a Molex 39-01-0023 or equivalent. The mating connector also requires two Molex 39-01-0031 terminals or equivalent.
B. Specifications J4 (Parallel I/O) J4 is a 50-pin (dual 25-pin) vertical male header with 0.1 inch contact spacing. The 24 general purpose parallel I/O signals are included in this connector. The pin assignments are given in the “J4 Parallel I/O Pinout” table following. The pin assignments are chosen for direct connection to an I/O module mounting rack, such as those offered by Ziatech and Opto 22. The mating connector is a T&B Ansley #622-5030 or equivalent.
B. Specifications J5 (Memory Expansion) J5 is a 54-pin (dual 27-pin) socket with 0.1 inch contact spacing. J5 includes memory address, data, and control signals for supporting RAM memory expansion and Flash boot modules. The pin assignments are given in the "J5 Memory Expansion Pinout" table below. The mating modules are the Ziatech ZT 96047 for an additional 4 Mbytes of RAM and the Ziatech ZT 95190 for a flash boot module.
B. Specifications J6 (Local Bus) J6 is a 100-pin (dual 50-pin) vertical receptacle with 0.05 inch contact spacing. This connector includes the signals needed for a local bus interface. This interface is used by optional piggyback adapters, such as the Ziatech zVID video adapters. The pin assignments are given in the “J6 Local Bus Video Pinout” table below. The mating connector is an AMP 1-104655-1 (0.250 inch mated height), 1-10456-0 (0.320 inch mated height), or 1-104693-0 (0.0390 inch mated height).
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B. Specifications J7 (Auxiliary Power) J7 is a location for a 2-pin latching COMBICON connector with 0.2 inch contact spacing. J7 includes the power and ground connections needed to power the ZT 8904 when the STD bus connection is not used. The pin assignments are given in the following table, "J7 Auxiliary Power Pinout." The multiple-source board mount connectors and associated mating connectors are shown below. Board Connector Mating Connector Augat 5EHDV-02 Augat 5ESDV-02 Phoenix Contact MSTBVA2.
B. Specifications J8 (Optional IDE) J8 is an optional 44-pin (dual 22-pin) vertical receptacle with 2 mm contact spacing. An IDE interface is provided through this connector. The pin assignments are given in the "J8 Optional IDE Pinout" table below. The board connector is a SAMTEC STMM-12201-S-D-SM or equivalent.
B. Specifications J9 (Reserved) J9 is reserved for Ziatech test purposes. Cables The following cables are available from Ziatech Corporation.
B. Specifications 11" 9.5" MALES 40 80 FEMALES 11" TB ANSLEY 622-1030 10-Pin Female w/ Polarization (4 Places) AMP 104891-8 (2 Places) Terminating Covers AMP 104892-8 Receptacle w/ Latch TB ANSLEY 622-09PMI 9-Pin Male (4 Places) 1 6 9 COM 4 5 1 6 Notes: 1) On side of connector P1 heat dry permanently stamp the following text: 90200-0.
B. Specifications 11 1/2 " 1 1/2" RED WIRE PIN 1 J1 PIN 2 PIN 1 1-4 P1 SINGATRON DJ-002-B 5P DIN CONNECTOR HEAT SHRINK TUBING 1/2" DIAMETER BLACK ALPHA FIT 221-1/2 P2 HEAT SHRINK TUBING 1/16" DIAMETER BLACK ALPHA FIT 221-1/16 P1 KEYBOARD CONN. PIN ASSIGNMENT CHART J1 1 2 3 4 5 2 4 3 1 SHIELD - 3M 3625/14 GRAY 14 CONDUCTOR 1mm. CENTERS 28 GAUGE STRANDED FLAT CABLE OR EQUIV. NOTES: 1) PUT FLAT CABLE BETWEEN CONNECTOR BODY AND CAP ON UNUSED PINS TO MAINTAIN SPACING, ALIGNMENT AND RIGIDITY.
B. Specifications HIRSCHMANN #MAK 50 S (930172-517) FEMALE 5 PINS AT 180 DIN CONNECTOR 10" PIN 2 P1 1-4 5 - 14 P2 3M 3625/14 GRAY 14 CONDUCTOR 1mm. CENTERS 28 GAUGE STRANDED FLAT CABLE OR EQUIV. HEAT SHRINK TUBING 1/4" DIAMETER BLACK ALPHA FIT 221-1/4 P1 - KEYBOARD CONN. PIN ASSIGNMENT CHART RIBBON CABLE WIRE # 1 2 3 4 5 SHIELD 2 4 3 1 3 4 2 5 1 3 FRONT VIEW 1" 3" 1/2" P1 J1 P2 - VIDEO CONN.
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B. Specifications 11" 9.5" MALES 40 80 FEMALES 11" AMP 104891-8 (2 Places) Terminating Covers AMP 104892-8 Receptacle w/ Latch Notes: 1) On side of connector P1 heat dry permanently stamp the following text: 90203-0. TB ANSLEY 622-1030 10-Pin Female w/ Polarization (2 Places) 1 3" 1 COM 2 6 9 KEEP CABLE AS SINGLE PIECE FOR FIRST 3" BEFORE SEPARATING 5 COM 1 1 6 9 TB ANSLEY 622-09PMI 9-Pin Male (2 Places) Truncate Conductors 30, 40 After 10-Pin Female; Do Not Connect to 9-Pin Male.
C. PIA SYSTEM SETUP CONSIDERATIONS The 16C50A Parallel Interface Adapter (PIA) device used on the ZT 8904 is designed by Ziatech to offer bidirectional I/O signals with or without event sense capability. This device features low power, high speed, wide temperature operation achievable only by utilizing CMOS technology. Although CMOS technology offers many advantages, you must observe a few cautions when interfacing to any CMOS parts. CMOS inputs and outputs can exhibit latchup characteristics.
C. PIA System Setup Considerations Power Supply Sequence Mismatch A common application is to interface to a 24-position ZT 2226, Opto 22, or equivalent I/O module rack. Vcc and ground are provided from the ZT 8904 through connector J4 with Vcc protected by a 1 A fuse. This application is illustrated in Figure 1 below.
C. PIA System Setup Considerations One solution is to switch the external signals' power supply with an output that is controlled by the computer. In this manner, if the computer is off, so is the external power supply. This solution is illustrated in Figure 3 following. Custom Application ZT 8904 S 24 Power Supply 16C50A PIA Vcc External Power Supply 1Amp Interface Cable Figure 3.
C. PIA System Setup Considerations Signal Level Mismatch Power supplying the external signal in Figure 1 is always relative to the PIA input circuitry power because power is provided over the interface cable. Signal level mismatches will not occur and proper system operation will result. However, if separate power supplies are used, there are two predominant causes of signal level mismatches.
C. PIA System Setup Considerations ZT 8904 Power Supply Vcc 16C50A PIA 24-Position or Custom Application 24 External Power Supply Interface Cable Figure 7.
C. PIA System Setup Considerations Typically, optical isolators are used to help remove electrical noise while providing for different grounds. Separate grounds are achieved through the use of an additional power supply for the optocoupler rather than using the computer's power supply. If the computer's power supply powers the optocouplers, electrical isolation is defeated. An example of one such circuit is illustrated in Figure 8 below. The circuit can be altered to allow for design considerations.
C. PIA System Setup Considerations them to conduct and allowing the majority of energy to flow through them instead of through the diode clamps. The 39 pF capacitor, in conjunction with the ferrite bead, forms an additional low pass filter, and is entirely optional. The 1k Ω pullup ensures adequate rise time on the signal. The fuse acts as additional insurance against catastrophic events that might destroy the TransZorb and diode clamps.
D. CUSTOMER SUPPORT This appendix offers technical assistance and warranty information for this product, and also the necessary information should you need to return a Ziatech product. TECHNICAL/SALES ASSISTANCE If you have a technical question, please call Ziatech's Customer Support Service at the number below, or e-mail our technical support team at tech_support@ziatech.com. Ziatech also maintains an FTP site located at ftp://ziatech.com/Tech_support.
D. Customer Support Once you have an RMA number, follow these steps to return your product to Ziatech: 1. Contact Ziatech for pricing if the warranty expired. 2. Supply a purchase order number for invoicing the repair if the warranty expired. 3. Pack the board in anti-static material and ship in a sturdy cardboard box with enough packing material to adequately cushion it. Note: Any product returned to Ziatech improperly packed will immediately void the warranty for that particular product! 4.
D. Customer Support TRADEMARKS AT® is a registered trademark of IBM. Intel® and Intel386® are registered trademarks of Intel Corporation. Motorola® is a registered trademark of Motorola, Incorporated. MS-DOS® is a registered trademark of Microsoft Corporation. Opto 22® is a registered trademark of Opto 22. OS/2® is a registered trademark of IBM, Incorporated. QNX® is a registered trademark of Quantum Software Systems Ltd. STD 32® is a registered trademark of Ziatech Corporation.
1050 Southwood Drive San Luis Obispo, CA 93401 USA Tel: (805) 541-0488 FAX: (805) 541-5088 E-Mail: tech_support@ziatech.com Internet: http://www.ziatech.
