Specifications

Processor Description (V40)
OVERVIEW
The NEC 70208, commonly known as the V40, is a CMOS micro-
processor with a 16-bit internal and 8-bit external data bus structure.
The V40 instruction set includes all of the instructions of the 8088 and
80188 microprocessors, plus a few more. The added instructions
include string I/O, expanded rotate and shift, bit and nibble
manipulation, BCD arithmetic, and 8080 emulation mode.
The V40 contains several peripherals frequently used in STD bus
applications. These peripherals include a serial controller, interrupt
controller, direct memory access (DMA) controller, counter/timers,
and a programmable wait-state generator.
This chapter divides the V40 microprocessor into functional blocks
and presents an overview of each. More detailed descriptions of the
programmable functional blocks are found in subsequent chapters.
ZT 8832 SPECIFICS
The V40 includes a dynamic RAM (DRAM) refresh controller for
applications supporting DRAM devices. Since the ZT 8832 contains
only static RAM, the refresh controller is not needed.
The V40 includes four DMA channels. The ZT 8832 makes use of
one of these channels to provide high speed data transfers between I/O
on the SBX expansion module and dual port or local RAM. The
remaining three channels are not supported by the ZT 8832.
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