Specifications

Theory of Operation
possible for the STD bus CPU to perform these writes as two
sequential operations, the SBX expansion module interface requires a
15 µs reset pulse width.
In response to all other reset sources, the ZT 8832 enters a reset state
that typically lasts 600 ms (worst-case specifications are 250 ms
minimum and 1000 ms maximum). The following events occur
during the reset period:
• The STD bus control port and local control port are reset to a
logical 0 during power up, STD bus SYSRESET*, local
pushbutton reset, and watchdog timer stage 2 timeout.
• If the Board Select Port is jumper enabled, the board is de-
selected during power-up. The Board Select Port is unaffected
by any other source of reset.
• The dual port RAM controller is reset by all of the above
sources of reset. Data being transferred to or from the dual port
RAM at the time of reset will be corrupted. If the STD bus CPU
attempts a dual port RAM access while the controller is in reset,
it is held off until the reset period is complete. This will cause
problems in systems that have critical interrupt latencies, DMA
latencies, asynchronous data transfers, or dynamic RAM that
must be refreshed by the STD bus CPU.
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