Specifications

Theory of Operation
RESET
The ZT 8832 is reset by any of the following events:
• Programming the STD bus control port with a 0Fh, followed by
a logical 0, from the STD bus CPU. This resets the ZT 8832
only. The STD bus is not affected.
• Activating the pushbutton switch located on the ZT 8832. This
resets the ZT 8832 only. The STD bus is not affected.
• Dropping Vcc applied to the ZT 8832 through pins 3 and 4 of
the STD bus connector to below a typical value of 4.37 V (worst
case specifications are 4.49 V maximum and 4.25 V minimum).
This resets the ZT 8832 only. The STD bus is not affected.
• Failure to strobe the watchdog timer during stage 2 time delay.
This is an optional source of reset. If the two-stage watchdog
timer is enabled, it generates a non-maskable interrupt if it is not
strobed within the first-stage time out period. If the non-
maskable interrupt service routine does not strobe the watchdog
timer within the second-stage time out period, a local reset is
generated. This resets the ZT 8832 only. The STD bus is not
affected.
• An active low on pin 47 (SYSRESET*) of the STD bus. The
STD bus CPU typically drives SYSRESET* to a logical 0 when
it is being reset. In response to a SYSRESET*, the ZT 8832
drives STD bus pin 48 (PBRESET*) to a logical 0 to prevent the
STD bus CPU from coming out of reset and attempting an
access to a ZT 8832 still in reset. An STD bus CPU is typically
held in reset by an active PBRESET*. In a system with multiple
ZT 8832s, PBRESET* is held active until the last ZT 8832 is
out of reset and operational.
In response to the STD bus control port reset, the ZT 8832 enters a
reset state for a variable time period. The ZT 8832 enters reset a
maximum of 250 ns after a 0Fh is written to the control port and
remains reset until a logical 0 is written to the control port. While it is
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