Specifications

Theory of Operation
The simplest interrupt architecture is one in which the ZT 8832 does
not share the interrupt with any other STD bus boards, including other
ZT 8832s. For this architecture, an interrupt cycle is outlined below.
• The local CPU activates the STD bus interrupt request by
writing to the local control port. Please note that the STD bus
CPU must first remove the interrupt mask by writing to the STD
bus control port.
• The STD bus CPU responds to the interrupt request by vectoring
to the dedicated interrupt service routine.
• The interrupt service routine resets the interrupt request by
writing to the STD bus control port. To prevent missing a
subsequent interrupt, it is best to reset the request as early as
possible.
The ZT 8832 provides an Interrupt Status Port if it is necessary to
share the ZT 8832 interrupt with other STD bus boards, including
other ZT 8832s. The Interrupt Status Port, shown in Figure 3-4,
provides a means by which the STD bus CPU can determine, in
general, if any of the shared resources generated an interrupt request,
and specifically, if the ZT 8832 generated an interrupt request.
Register:Interrupt Status Port (ISP)
Address:38h
Access:Read
76543210
LS
Local Interrupt Status
0 No interrupt
1 Interrupt
SS
STD Bus Interrupt Status
0 No interrupt
1 Interrupt
——————
Figure 3–4. Interrupt Status Port Architecture.
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