Specifications

Theory of Operation
STD BUS INTERRUPTS
The ZT 8832 is capable of generating maskable and non-maskable
interrupts to the STD bus CPU. The maskable interrupt is jumper
selectable to the STD bus INTRQ* (pin 44), INTR1* (pin 37), or
INTRQ2* (pin 50). The non-maskable interrupt is dedicated to the
STD bus NMIRQ* (pin 46). This section discusses the issues
surrounding the use of the ZT 8832 and STD bus interrupts.
The local CPU generates a non-maskable interrupt to the STD bus
CPU by writing to the local control port. The ZT 8832 does not
provide any status to the STD bus master to indicate that it generated
the non-maskable interrupt. If it is necessary to distinguish between
multiple sources of non-maskable interrupt, the application software
can implement a status byte in the dual port RAM. In general, non-
maskable interrupts are reserved for orderly shutdown of a system in
response to a catastrophic event.
There are several issues surrounding the use of maskable interrupts.
The first thing to determine is which STD bus interrupts are supported
by the STD bus CPU. Most STD bus CPU boards support INTRQ*;
many of the newer models also support INTRQ1* and INTRQ2*. For
example, the ZT 8806/8807 supports INTRQ*, while the
ZT 8808/8809 and ZT 8816/8817 (revision B and later) support
INTRQ*, INTRQ1*, and INTRQ2*. If the STD bus CPU supports
more than one interrupt request, the next thing to determine is which
to use. The best choice is to use an interrupt request that is not shared
with other STD bus boards. This greatly simplifies the application
software. Once the STD bus interrupt request is selected, the ZT 8832
must be jumper configured to support it.
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