Specifications

Theory of Operation
writes to the LMI bit are ignored until the interrupt request is cleared
by the STD bus CPU writing a logical 1 followed by a logical 0 to the
SMR bit of the STD bus control port.
The Local Bus Control Port Non-Maskable Interrupt (LNI) bit (bit 1)
is programmed by the local CPU to generate a non-maskable interrupt
to the STD bus CPU. The local CPU generates a non-maskable
interrupt to the STD bus CPU by writing a logical 1 followed by a
logical 0 to the LNI bit. The ZT 8832 does not provide any status to
the STD bus CPU that flags an active non-maskable interrupt request.
If this is necessary for the application, a status word can be
implemented in the dual port RAM.
The Local Control Port Lock (LLK) bit (bit 2) is programmed by the
local CPU to prevent the STD bus CPU from accessing the dual port
RAM. The local CPU arms Lock by programming the LLK bit with a
logical 1. At this point, the STD bus CPU can still access the dual
port RAM. It is not until the local CPU performs the first read, or a
write of the dual port RAM, that the STD bus CPU is no longer
granted access. Any attempt by the STD bus CPU to access dual port
RAM is denied, suspending STD bus CPU operation until the local
CPU programs LLK with a logical 0.
The Local Control Port Maskable Interrupt Reset (LMR) bit (bit 3) is
programmed by the local CPU to reset an active maskable interrupt
request generated by the STD bus CPU through the SMI bit of the
STD bus control port. The local CPU must first program the LMR bit
with a logical 0 to enable the STD bus CPU to generate a maskable
interrupt. To reset an active maskable interrupt, the local CPU must
program the LMR bit with a logical 1 followed by a logical 0.
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