Specifications

Theory of Operation

Local Control Port Architecture

Figure 3-2 shows the architecture of the local control port. Bit

definitions are given on the following pages.

Note: The STD bus cannot be reset through the local control port. All

other functions are symmetrical between the STD bus control port and

the local control port.

Address:230h

Access:Write

76543210

LMI

Maskable Interrupt to STD Bus CPU

0 No interrupt

1 Interrupt

LNI

Non-Maskable Interrupt to STD Bus

CPU

0 No interrupt

1 Interrupt

LLK

Lock Out STD Bus CPU Dual Port

Access

0 No lock

1 Lock

LMR

Reset Local CPU Maskable Interrupt

Request

0 No reset

1 Reset

————

Figure 3–2. Local Control Port Architecture.

The Local Control Port Maskable Interrupt (LMI) bit (bit 0) is

programmed by the local CPU to generate a maskable interrupt to the

STD bus CPU. The LMI bit is connected to the STD bus INTRQ*

(pin 44), INTRQ1* (pin 37), or INTRQ2* (pin 50) through jumper

selection. Before the LMI bit is programmed, the STD bus CPU must

program the SMR bit of the STD bus control port with a logical 0.

Once this is done, the local CPU generates a maskable interrupt to the

STD bus CPU by writing a logical 1 to the LMI bit of the local

control port. After a logical 1 is written by the local CPU, all other

3-13