Specifications

Theory of Operation
The STD Bus Control Port Maskable Interrupt Reset (SMR) bit (bit 3)
is programmed by the STD bus CPU to reset an active STD bus
maskable interrupt request generated by the local CPU through the
LMI bit of the local control port. The Interrupt Status Port (ISP) is
available to the STD bus CPU to determine if the local control port
LMI bit is active. The STD bus CPU must first program the SMR bit
with a logical 0 to enable the local CPU to generate a maskable
interrupt. To reset an active maskable interrupt, the STD bus CPU
must program the SMR bit with a logical 1 followed by a logical 0.
STD Bus Control Port Programmable Reset
The STD bus CPU resets the local CPU by writing a 0Fh to the STD
bus control port followed by a logical 0. This software programmable
reset does not affect the STD bus. The ZT 8832 enters reset a
maximum of 250 ms after the 0Fh is written and remains reset until
the logical 0 is written. The STD bus CPU should not access the
ZT 8832 before the logical 0 is written.
Local Control Port
Overview
The local control port is an I/O mapped device programmed by the
local CPU to perform the following operations.
• Generate maskable and non-maskable interrupts
• Lock dual port access
• Reset the maskable interrupt generated by the STD bus CPU
The local control port does not have readback and is not accessible by
the STD bus CPU.
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