Specifications

Theory of Operation
• Program the interrupt controller to enable IR5, as discussed in
Chapter 8;
• Remove the hardware mask by programming the LMR bit of the
local control port with a logical 0.
After the local CPU has performed these operations, the STD bus
CPU generates a maskable interrupt to the local CPU by writing a
logical 1 to the SMI bit of the STD bus control port. After a logical 1
is written by the STD bus CPU, all other writes to the SMI bit are
ignored until the interrupt request is cleared by the local CPU writing
a logical 1 followed by a logical 0 to the LMR bit of the local control
port.
The STD Bus Control Port Non-maskable Interrupt (SNI) bit (bit 1) is
programmed by the STD bus CPU to generate a non-maskable
interrupt to the local CPU. The STD bus CPU generates a non-
maskable interrupt to the local CPU by writing a logical 1 followed
by a logical 0 to the SNI bit. The SNI bit shares the non-maskable
interrupt with the jumper selectable watchdog timer and the optional
numeric data processor. While there is no status available to the local
CPU that indicates SNI is active, there is status for both the watchdog
timer and the numeric data processor. This means that if more than
one of the non-maskable interrupt sources is used, the local CPU can
determine that the SNI bit generated a request by eliminating the other
possible sources through polling.
The STD Bus Control Port Lock Dual Port Access (SLK) bit (bit 2) is
programmed by the STD bus CPU to prevent the local CPU from
accessing the dual port RAM. The STD bus CPU arms Lock by
programming the SLK bit with a logical 1. At this point, the local
CPU can still access the dual port RAM. It is not until the STD bus
CPU performs the first read, or a write of the dual port RAM, that the
local CPU is no longer granted access. Any attempt by the local CPU
to access dual port RAM is denied, suspending local CPU operation
until the STD bus CPU programs SLK with a logical 0.
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