Specifications

Theory of Operation
STD Bus Control Port Architecture
Figure 3-1 shows the architecture of the STD bus control port. Bit
definitions are given on the following pages.
Note: Writing a 0Fh followed by a logical 0 to the STD bus control
port resets the ZT 8832.
Register:STD Bus Control Port
Address:30h
Access:Write
76543210
SMI
Maskable Interrupt to Local CPU
0 No interrupt
1 Interrupt
SNI
Non-Maskable Interrupt to Local CPU
0 No interrupt
1 Interrupt
SLK
Lock Out Local CPU Dual Port
Access
0 No lock
1 Lock
SMR
Reset STD Bus Maskable Interrupt
Request
0 No reset
1 Reset
————
Figure 3–1. STD Bus Control Port Architecture.
The STD Bus Control Port Maskable Interrupt (SMI) bit (bit 0) is
programmed by the STD bus CPU to generate a maskable interrupt to
the local CPU. The SMI bit is connected to interrupt request 5 (IR5)
of the interrupt controller. The local CPU must complete the
following operations before the SMI bit is active:
• Enable the interrupt controller with the OPCN V40 configura-
tion register, as discussed in Chapter 6;
3-10