Specifications

Theory of Operation
3. Can the ZT 8832 access STD bus memory and I/O?
The ZT 8832 includes 32 Kbytes of dual port RAM mapped into
the STD bus memory addressing space. This is the only STD
bus memory accessible by the local CPU. The local CPU does
not have access to any STD bus I/O.
4. Can the STD bus CPU access memory and I/O local to the
ZT 8832?
The STD bus CPU has access to 32 Kbytes of dual port RAM
local to the ZT 8832. The three 32-pin JEDEC sockets are not
available to the STD bus CPU. The ZT 8832 includes 16 I/O
ports that are accessible by the STD bus CPU. This I/O is
divided into the STD bus control port, board select port, and
interrupt status port. This is the only I/O on the ZT 8832
available to the STD bus CPU.
5. How does the ZT 8832 compare with Ziatech’s earlier I/O
control processor, the ZT 8830?
The ZT 8832 and ZT 8830 are both designed to increase the
modularity and performance of STD bus applications through
parallel processing. Both boards include 32 Kbytes of dual port
RAM accessible by both the STD bus CPU and the CPU local to
the board. Both boards also include an SBX expansion module
for I/O expansion with off-the-shelf or custom I/O. It should be
noted that the SBX expansion module connector is in the same
place on both boards; this permits custom SBX designs for the
ZT 8830 to be used on the ZT 8832.
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