Specifications

Getting Started
I/O
The ZT 8832 includes some I/O devices addressable by the local CPU
and other I/O devices addressable by the STD bus CPU. This is
shown in two I/O maps. Figure 2-6 illustrates the devices accessible
by the local CPU. Figure 2-5 illustrates the devices available to the
STD bus CPU. Note that none of the I/O devices are accessible from
both the local CPU and the STD bus CPU.
FFFFh
8000h
7FFFh
0000h
Not Used
Board Select (Write)
Interrupt Status (Read)
Not Used
7FF0h
7FEFh
STD Bus Control Port
7FF8h
7FF7h
Figure 2–5. STD Bus CPU I/O.
Several I/O devices available to the local CPU must be enabled and
mapped by programming the V40 configuration registers. These
devices are the interrupt controller, counter/timers, DMA controller,
and V40 serial controller. The address mapping of all other local I/O
devices is fixed to the locations shown in Figure 2-6. Note that these
I/O devices are not accessible by the STD bus CPU.
The ZT 8832 requires 16 consecutive STD bus I/O port addresses.
The STD bus control port is a single byte value redundantly mapped
over the lower eight addresses. The STD bus control port can only be
written; no readback is available. The upper eight addresses are
shared between the Board Select and Interrupt Status Port. Both the
Board Select and Interrupt Status Ports are redundantly mapped single
byte values. The Board Select Port can only be written; no readback
is available. The Interrupt Status Port can only be read.
2-12