Specifications

Specifications
TIMING
The ZT 8832 meets the timing requirements outlined in the STD 32
bus specification. The SBX expansion module timings are given on
the following pages. These pages assume the WCY1 and WCY2 V40
configuration registers are programmed to insert two wait states for all
I/O and DMA transfers.
MA0-MA2
VALID
t2
MCS*
MWAIT*
IORD*
MD0-MDF
VALID
t8t19 t17
t3
t5
t4
t24
t1
t7
Symbol Parameter Min Max
t1 Address setup to read low 50
t2 Address hold from read high 30
t3 Read pulse width 300
t4 Data delay from read low 0 250
t5 Data float after read high 0 80
t7 Chip select setup to read low 25
t8 Chip select hold from read high 30
t17 Wait request pulse width 0 4 ms
t19 Wait request delay from chip select 0 75
t24 Data hold from wait request 0
All times given in nanoseconds except where otherwise indicated
Figure B–11. SBX Expansion Module Read Timing.
B-22