Specifications

Specifications
Notes:
[1] Signals ending with an asterisk are active low and signals without an asterisk are
active high.
[2] The V40 clock is optionally connected to MCLK with CT1 and CT2 (refer to the
cuttable trace description on page A-17). This option is useful for designing SBX
expansion modules synchronous to the ZT 8832 CPU.
[3] These signals are not supported. The MPST* is a no-connect and TDMA is
grounded.
[4] These signals provide additional address lines to the three supported in the
expansion module specification. This feature is supported with CT5 through CT8
as defined in the cuttable trace table starting on page A-16.
[5] Interrupt 1 is routed to IRQ3 of the V40 interrupt controller and Interrupt 0 is
routed to IRQ2 of the V40 interrupt controller.
[6] The I/O address range for Chip Select 0 is 2F8h through 2FFh and the I/O
address range for Chip Select 1 is 300h through 307h. If more than the three
standard I/O address lines are used, Chip Select 0 grows downward and Chip
Select 1 grows upward.
[7] DMA is supported through channel 0 of the V40 DMA controller.
Table B-8
J5 Serial Port Pinout.
Pin Signal Description
1 RxD Receive Data
2 TxD Transmit Data
3 GND Ground
Note: The pin assignments enable the ZT 90069 cable to connect J5 directly to a
male 25-pin D shell connector.
B-16