Specifications

Watchdog Timer
Programming
The watchdog timer is armed and strobed with the most significant
parallel I/O signal. The watchdog timer is armed with the following
programming sequence.
1. Initialize the most significant bit of the parallel ports (I/O port
address 220h, bit 7) with a logical 0.
2. Enable the parallel ports by writing a logical 1 to the 82050
OUT2 bit (I/O port address 3FCh, bit 3).
3. Arm the watchdog timer by programming the most significant
bit of the parallel ports with a logical 1.
The watchdog timer is strobed with the following programming
sequence.
1. Disarm the watchdog timer by writing a logical 0 to the most
significant bit of the parallel ports.
2. Rearm the watchdog timer by writing a logical 1 to the most
significant bit of the parallel ports.
In addition to the watchdog timer non-maskable interrupt, the
ZT 8832 also supports 8087 Numeric Data Processor and STD bus
control port non-maskable interrupts. If more than one source of non-
maskable interrupt is used in an application, the non-maskable
interrupt service routine must be able to identify the source of the
interrupt.
The watchdog timer non-maskable interrupt request is also routed into
IRQ1 of the interrupt controller. This enables the non-maskable
interrupt service routine to read the interrupt controller to determine if
the watchdog timer has generated a non-maskable interrupt request.
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