Specifications

Watchdog Timer
Multiple Stages
Many watchdog timers are implemented with a single stage that
generates a reset if allowed to time out. The problem with this
implementation is that the CPU does not have advance warning of the
reset. Without advance warning, the CPU cannot take corrective
action that includes, as a minimum, setting a flag indicating that a
system failure has occurred.
Other watchdog timers are implemented with a single stage that
generates a non-maskable interrupt if allowed to time out. The
problem with this implementation is that the pointer to the non-
maskable interrupt service routine is generally stored in RAM that can
be overwritten by a CPU not operating as programmed.
The solution to these problems is to implement a two-stage watchdog
timer such as the one found on the ZT 8832. If the first stage times
out, a non-maskable interrupt is generated to invoke a service routine
that takes the necessary corrective action. If the second stage times
out, a local reset is generated to put the ZT 8832 in a known operating
state.
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