Specifications

Watchdog Timer
OPERATION
In operation, the local CPU is programmed to strobe the watchdog
timer at a periodic rate less than the stage 1 time delay. If the local
CPU fails to operate as programmed, stage 1 of the watchdog timer
generates a non-maskable interrupt. The non-maskable interrupt ser-
vice routine takes the necessary corrective action that includes
strobing the watchdog timer before the stage 2 time delay to prevent a
local reset. If the local reset is desired, the non-maskable interrupt
service routine simply does not strobe the watchdog timer.
Reset
The watchdog timer is disarmed during and after both a power-up and
reset condition.
Stage 2 of the watchdog timer generates a local reset if allowed to
time out. This reset period lasts for up to 1 second. Since the STD bus
CPU is unaffected by this reset, it might attempt an I/O or dual port
access to the ZT 8832. If this occurs, the operation of the STD bus
CPU is suspended until the reset period is over. This suspension will
cause problems in a system having critical interrupt latencies, DMA
latencies, asynchronous data transfers, or dynamic RAM that must be
refreshed by the STD bus CPU.
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