Specifications

Parallel I/O
OPERATION
Reset
The parallel port outputs are disabled and passively pulled to a TTL
high after power up or reset.
Programming the Parallel
Ports
The parallel ports are enabled by writing a logical 1 to the 82050
serial port OUT2 bit (I/O port address 3FCh, bit 3). This operation
immediately transfers the contents of the parallel ports to the J1
connector. The contents of the parallel ports are not defined after
power-up. Therefore, it is recommended that all 24 bits be initialized
with logical 0s before the parallel port outputs are enabled. This
initialization does the following:
• Maintains the power-up and reset state of a TTL high at
connector J1.
• Prevents contention with external devices driving the parallel
I/O signals.
• Ensures that a jumper selected watchdog timer is not armed.
Once enabled, the parallel port bits are programmed with standard
input and output instructions. The parallel ports are inverting so that
data written to the parallel port appears in the opposite state at
connector J1 and data read from the parallel port reflects the inverted
state of the data at connector J1.
The V40 supports string I/O instructions for transferring data between
the parallel I/O and memory at rates of up to 1 Mbyte/second. The
high throughput of these instructions occurs because the memory
address is automatically incremented or decremented after each
transfer.
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