Specifications

Parallel I/O
Output Buffer
The Output Buffer isolates the Output Latch from connector J1. The
Output Buffer is disabled and enabled with the 82050 Serial Port
OUT2 bit. The OUT2 connection ensures that the Output Buffer is
disabled during and after power-up to prevent the I/O signals at
connector J1 from glitching. The OUT2 signal also disables the
Output Buffer during and after a reset.
The Output Buffer is an inverting open collector device. The
inversion means that a logical 0 written to the parallel port appears as
a TTL high at the J1 connector and a logical 1 written to the parallel
port appears as a TTL low at the J1 connector. It is the open collector
feature that permits each parallel I/O signal to be configured as an
input. To use the parallel I/O signal as input, a logical 0 must first be
written to the Output Latch to open collect the Output Buffer and
prevent contention with the input signal.
Input
Buffer
The Input Buffer is enabled during read operations to transfer the data
from connector J1 to the internal data bus. If the parallel port bit is
configured as output, the data read is the last data written to the
parallel port bit. If the parallel port is configured as input, the data
read is the data driven by an external device.
The Input Buffer is an inverting device. This means that data read
from the parallel port as a logical 0 is actually a TTL high at
connector J1, and data read from the parallel port as a logical 1 is a
TTL low at connector J1.
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