Specifications

Serial Communications (82050)
The DCTS, DDSR, and DDCD bits (bits 0, 1, and 3) are set to a
logical 1 to indicate that the CTS, DSR, and DCD bits have changed
state since the last time the Modem Status register was read.
The TERI bit (bit 2) signals the trailing edge detection of the Ring
Indicator (RI). The TERI bit is a logical 1 if the RI input changed
from a spacing (positive) state to a marking (negative) state since the
last time the Modem Status register was read.
The CTS bit (bit 4) reflects the state of the Clear To Send (CTS)
signal. If CTS is in the marking state, the CTS bit is a logical 0. If
CTS is in the spacing state, the CTS bit is a logical 1. During
loopback mode, the CTS bit is internally connected to RTS.
The DSR bit (bit 5) reflects the state of the Data Set Ready (DSR)
signal. If DSR is in the marking state, the DSR bit is a logical 0. If
DSR is in the spacing state, the DSR bit is a logical 1. During
loopback mode, the DSR bit is internally connected to DTR.
The RI bit (bit 6) reflects the state of the Ring Indicator (RI) signal. If
RI is in the marking state, the RI bit is a logical 0. If RI is in the
spacing state, the RI bit is a logical 1.
The DCD bit (bit 7) reflects the state of the Data Carrier Detect
(DCD) signal. If DCD is in the marking state, the DCD bit is a logical
0. If DCD is in the spacing state, the DCD bit is a logical 1.
11-16