Specifications

Serial Communications (82050)
The RTS bit (bit 1) defines the state of the Request To Send (RTS)
signal. Programming the RTS bit with a logical 0 forces RTS to a
marking (negative) state, and programming the RTS bit with a
logical 1 forces RTS to a spacing (positive) state.
Bit 2 is permanently set to logical 0.
The OUT2 bit (bit 3) defines the state of the Output 2 (OUT2) signal.
The OUT2 signal is connected to the output control of the three
parallel ports available at connector J1. Programming OUT2 with a
logical 0 disables the parallel ports, and programming OUT2 with a
logical 1 enables the parallel ports. The power-on state of OUT2
disables the parallel ports.
The LOOP bit (bit 4) selects the internal loopback operation of the
ACC. Programming LOOP with a logical 0 disables loopback, and
programming LOOP with a logical 1 enables loopback. With loop-
back enabled, the following takes place:
– The RxD input is ignored.
– The TxD output is externally set to the marking (logical 1) state
and internally connected to RxD.
– The modem control inputs (CTS, DSR, DCD, and RI) are
ignored.
– The modem control outputs (DTR, RTS, and OUT2) are
externally forced to a logical 1 and internally connected to the
modem control inputs.
– The receiver and transmitter interrupts are fully functional.
During loopback, the data transmitted is immediately received.
Bits 5-7 are permanently set to logical 0.
11-14