Specifications

Serial Communications (82050)
The DR bit indicates the state of the ACC Receive Buffer. A logical 1
in the DR bit signals the availability of a character in the Receive
Buffer. The DR bit is automatically reset to a logical 0 when the
Receive Buffer is read.
The OE, PE, and FE bits are transmission error indicators. An
overrun error is indicated by a logical 1 in the OE bit, a parity error is
indicated by a logical 1 in the PE bit, and a framing error is indicated
by a logical 1 in the FE bit. In all cases, the error indicator is reset
when the Line Status register is read. An overrun error is generated
when a character is written into the Receive Buffer before the
previous character is read by the CPU. A parity error is generated
when the received character does not have the correct even or odd
parity. A framing error indicates that the received character does not
have a valid stop bit. Any of these error bits are capable of generating
an interrupt if enabled through the Interrupt Enable register.
The BI bit is set to a logical 1 when the RxD signal is held in the
marking (negative) state for longer than a single character trans-
mission (including start, data, parity, and stop bits). Bit four is reset to
a logical 0 when the Line Status register is read. This bit is capable of
generating an interrupt if enabled through the Interrupt Enable
register.
The THRE and TEMT bits provide Transmitter status. A logical 1 in
the THRE bit signals that the Transmit Buffer is empty and ready to
receive a new character for transmission. This bit is capable of
generating an interrupt if enabled through the Interrupt Enable
register. TEMT is similar to bit 5 except that bit 6 is not set to a
logical 1 until both the Transmit Buffer and Transmit Shift register are
empty. Both THRE and TEMT bits are automatically reset to a
logical 0 with the loading of the next character to be transmitted.
Bit 7 is permanently set to logical 0.
11-12