Specifications

Serial Communications (82050)
Line Status
The Line Status register, shown in Figure 11-3, provides information
to the CPU concerning the data transfer. Reading the Line Status
register clears bits 1 through 4 (OE, PE, FE, and BI).
Register:Line Status
Address:03FDh
Access:Read
76543210
DR
Data Ready
0 No character available
1 Character available
OE
Overrun Error
0 No error
1 Error
PE
Parity Error
0 No error
1 Error
FE
Framing Error
0 No error
1 Error
BI
Break Interrupt
0 No break
1 Break
THRE
Transmitter Holding Register
0 Full
1 Empty
TEMT
Transmitter Empty
0 Full
1 Empty
0
Figure 11–3. Line Status Register.
11-11