Specifications

Serial Communications (V40)

Enabling even or odd parity is the function of the PS field. Parity is

disabled if a logical 0 is written to bit 4. If parity is disabled, the

parity bit will not be appended to the characters transmitted and the

characters received will not be tested. If bit 4 is a logical 1, parity is

enabled. Bit 5 selects between even or odd format. A character has

even parity if it includes an even number of bits set to a logical 1. A

character has odd parity if it includes an odd number of bits set to a

logical 1.

The number of stop bits appended to the character during transmission

or stripped off during reception is defined by the STL bit field. The

choice is between one or two stop bits.

Serial Interrupt Mask Register

(SIMK)

The SCU is capable of interrupting the CPU when a character is

received into the Serial Receive Buffer or transmitted out of the Serial

Transmit Buffer. The SIMK register includes two programmable bits,

as illustrated in Figure 10-5, to enable the interrupts. Setting the RM

bit to a logical 1 prevents the SCU from generating an interrupt when

a character is received. A logical 0 in the RM bit enables the interrupt.

The TM bit provides the same control for transmitted characters.

Address:Base + 3

Access:Read/Write

76543210

Receiver Mask

0 Unmask

1 Mask

Transmitter Mask

0 Unmask

1 Mask

——————

Figure 10–5. Serial Interrupt Mask Register.

10-10