Specifications

Serial Communications (V40)
error conditions occur and remain set until a logical 1 is written to the
ECL bit.
Serial Mode Register
(SMD)
Figure 10-4 shows the format for the SMD register. This register
includes all the functions that are not likely to change after they have
been initialized. Bits 1 and 2 combine to define the clock divisor for
the baud rate. Programming the baud rate is defined in more detail on
page 10-13.
The character length is programmed with the CL field. If a character
length of seven is selected, the SCU transmits the lower seven bits of
the 8-bit character written by the CPU. Characters read by the CPU
will have a logical 0 in the most significant bit position.
Register:Serial Mode (SMD)
Address:Base + 2
Access:Write
76543210
BF
Baud Rate Factor
00,01 Illegal
10 RTCLK frequency ÷ 16
11 RTCLK frequency ÷ 64
CL
Character Length
00,01 Illegal
10 7-bit characters
11 8-bit characters
PS
Parity Select
00,10 No Parity
01 Odd parity
11 Even parity
STL
Stop Bit Length
00,10 Illegal
01 1 stop bit
11 2 stop bits
Figure 10–4. Serial Mode Register.
10-9