Specifications

Serial Communications (V40)
Serial Command Register (SCM)
Figure 10-3 illustrates the SCM register bit map. The SCU is config-
ured with the SCM and the SMD registers. The SCM register
includes the functions that are most likely to be modified during
operation. The SMD register will more than likely be programmed
just once for initialization.
Register:Serial Command (SCM)
Address:Base + 1
Access:Write
76543210
TE
Transmitter Enabled
0 Transmitter disabled
1 Transmitter enabled
—RE
Receiver Enabled
0 Receiver disabled
1 Receiver enabled
SBRK
Send Break
0 Normal operation
1 TxD = 0 (break)
ECL
Error Clear
0 No operation
1 Error flag clear
———
Figure 10–3. Serial Command Register.
Bits 0 and 2 are the Transmitter and Receiver control bits. Setting TE
to a logical 1 enables the transmitter and a logical 0 disables it. If TE
is reset during transmission, the data in the Serial Transmit Buffer will
be sent before transmission stops and TxD goes to a high level.
Setting the RE bit to a logical 1 enables the receiver and resetting the
RE bit disables it.
A break sequence is transmitted if the SBRK bit is set to a logical 1.
This mode of operation is independent of the Receiver Enable bit.
The break sequence is transmitted until SBRK is reset.
The ECL bit is used to reset the parity, overflow, and framing error
bits of the Serial Status register. These bits are set to a logical 1 if
10-8