Specifications

Serial Communications (V40)
Serial Status Register (SST)
Figure 10-2 shows the architecture of the SST register, which can be
read at any time.
Register:Serial Status (SST)
Address:Base + 1
Access:Read
76543210
TBR
Transmit Buffer Ready
0 STB full
1 STB empty
RBR
Receive Buffer Ready
0 SRB empty
1 SRB full
1PE
Parity Error
0 No error
1 Error occurred
OVE
Overrun Error
0 No error
1 Error occurred
FE
Framing Error
0 No error
1 Error occurred
BKD
Break
0 Normal reception
1 Break detected
1
Figure 10–2. Serial Status Register.
The first two bits define the state of the STB (Serial Transmit Buffer)
and SRB (Serial Receive Buffer). TBRDY (Transmit Buffer Ready)
is set to a logical 1 when a character is transferred out of the STB.
Application software uses TBRDY to determine when it is clear to
send a new character to the STB. TBRDY is automatically reset when
a new character is transferred into the STB. The RBRDY (Receive
10-6