Specifications

Serial Communications (V40)
Read/Write Control
The Read/Write Control block acts as an interface between the
internal registers of the SCU and the CPU. The control signals input
to the Read/Write Control logic, select internal registers, and control
the transfer of information between the CPU and the SCU.
Receiver
The Receiver block converts serial data input on the RxD signal to a
parallel format with the start, stop, and parity bits removed. The
parallel data is placed in the Serial Receive Buffer, and the Receive
Buffer Ready bit in the Serial Status register is set to a logical 1.
Activating the Receive Buffer Ready bit generates an interrupt if the
interrupts are not masked. The Receiver is also responsible for testing
data parity and monitoring for a Receive Break.
T
ransmitter
The Transmitter block converts the contents of the Serial Transmit
Buffer from a parallel format into a serial string. Start, stop, and
parity bits are added, as specified by the programmer in the Serial
Mode register. Next, the modified serial string is transmitted out of
the TxD signal at a rate equal to 1/16 or 1/64 that of the
Receiver/Transmitter Clock, also defined in the Serial Mode register.
The Transmit Buffer Ready bit in the Serial Status register is set to
alert the application program that it is clear to send the next character.
Activating the Transmit Buffer Ready bit generates an interrupt if the
interrupts are not masked by the Serial Interrupt Mask register.
Interrupt Generation
Logic
The Interrupt Generation Logic block can interrupt the CPU when
data is received into the Serial Receive Buffer or transmitted from the
Serial Transmit Buffer. These interrupts are used to vector the
application program to service routines that read a character from the
Serial Receive Buffer and write a character to the Serial Transmit
Buffer, respectively.
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