Specifications

DMA Controller (V40)

DMA Status (DST)

The Status register includes information about the currently

programmed state of the DMA channel. The format for DST is shown

in Figure 9-8. DST is accessed with the byte read instruction. The

TC0 bit indicates when the count register has reached zero and the

DMA transfer is completed. A logical 0 in TC0 means that the

operation has not been terminated and a logical 1 means that it has.

The RQ0 bit defines the state of the DMA request input. A logical 0

indicates no request active and a logical 1 indicates a request is

pending.

Address:Base +B

Access:Read Only

76543210

TC0

Terminal Count

0 Not ended (for each read)

1 END or terminal count

———RQ0

DMA Request

0 No DMA request active

1 DMA request active

———

Figure 9–8. DMA Status Register.

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