Specifications

DMA Controller (V40)

DMA Mode (DMD)

Figure 9-7 shows the format of the DMD register. The DMD register

can be accessed with byte or word instructions. The TDIR field

defines the mode of data transfer. A logical 0 in both bits selects the

verify operation. A logical 1 in bit 2 and a logical 0 in bit 3 selects

I/O-to-memory transfers. For memory-to-I/O transfers, bit 2 must be

programmed with a logical 0 and bit 3 with a logical 1.

Address:Base + A

Access:Read or Write

76543210

——

TDIR

Transfer Direction

00 Verify

01 I/O-to-memory

10 Memory-to-I/O

11 Not allowed

AUTI

Autoinitialize

0 Disable

1 Enable

ADIR

Address Direction

0 Increment

1 Decrement

TMODE

Transfer Mode

00 Demand

01 Single

10 Block

11 Not allowed

Figure 9–7. DMA Mode Register.

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