Specifications

DMA Controller (V40)

DMA Device Control (DDC)

Two DDC registers select various DCU operating modes. The format

for these registers is shown in Figure 9-6. These registers can be

accessed with byte or word operations. The DDMA bit can be set to a

logical 1 to prevent the DCU from requesting bus access. This should

be done when programming any of the DCU registers to prevent

incorrect DMA operation,

The WEV bit enables or disables wait states to be inserted by the V40

WCU during the verify operation. Programming WEV with a log-

ical 0 disables wait state insertion and programming a logical 1

enables it.

Address:Base + 8

Access:Read or Write

76543210

——

DDMA

Disable DMA Operation

0 Enable

1 Disable

——0——

Address:Base + 9

Access:Read or Write

76543210

—WEV

Wait Enable During Verify

0 Disable

1 Enable

——————

Figure 9–6. DMA Device Control Registers.

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