Specifications

Illustrations
Figure 7–8 Mode 1 Operation. ................................. 7-19
Figure 7–9 Mode 2 Operation.
................................. 7-21
Figure 7–10 Mode 3 Operation.
................................. 7-23
Figure 7–11 Mode 4 Operation.
................................. 7-25
Figure 7–12 Mode 5 Operation.
................................. 7-27
Figure 8–1 ICU Block Diagram.
................................. 8-4
Figure 8–2 Interrupt Initialization Programming.
.................. 8-8
Figure 8–3 Interrupt Initialization Word 1.
........................ 8-9
Figure 8–4 Interrupt Initialization Word 2.
....................... 8-10
Figure 8–5 Interrupt Initialization Word 3.
....................... 8-10
Figure 8–6 Interrupt Initialization Word 4.
....................... 8-11
Figure 8–7 Interrupt Mask Word.
............................... 8-12
Figure 8–8 Interrupt Priority and Finish Word.
................... 8-13
Figure 8–9 Interrupt Mode Word.
............................... 8-15
Figure 8–10 Interrupt Status Registers IRQ and IIS.
............... 8-17
Figure 8–11 Interrupt Status Register IPOL.
...................... 8-18
Figure 8–12 CPU Interrupt Vector Processing.
.................... 8-21
Figure 8–13 Nested Interrupt Structure.
.......................... 8-23
Figure 9–1 DCU Block Diagram.
................................ 9-4
Figure 9–2 DMA Initialization Command Register.
................ 9-8
Figure 9–3 DMA Channel Register.
.............................. 9-9
Figure 9–4 DMA Base and Current Count Registers.
............. 9-10
Figure 9–5 DMA Base and Current Address Registers.
............ 9-11
Figure 9–6 DMA Device Control Registers.
..................... 9-12
Figure 9–7 DMA Mode Register.
............................... 9-13
Figure 9–8 DMA Status Register.
.............................. 9-15
Figure 9–9 DMA Mask Register.
............................... 9-16
Figure 10–1 SCU Block Diagram.
............................... 10-3
Figure 10–2 Serial Status Register.
.............................. 10-6
Figure 10–3 Serial Command Register.
........................... 10-8
Figure 10–4 Serial Mode Register.
............................... 10-9
Figure 10–5 Serial Interrupt Mask Register.
..................... 10-10
Figure 10–6 SCU Serial Data Format.
........................... 10-12
Figure 11–1 ACC Block Diagram.
............................... 11-4
Figure 11–2 Line Control Register.
.............................. 11-9
Figure 11–3 Line Status Register.
............................... 11-11
Figure 11–4 Modem Control Register.
.......................... 11-13
Figure 11–5 Modem Status Register.
............................ 11-15
Figure 11–6 Divisor Latch.
.................................... 11-17
Figure 11–7 Interrupt Identify Register.
......................... 11-18
Figure 11–8 Interrupt Enable Register.
.......................... 11-19