Specifications

DMA Controller (V40)
Internal Bus Interface
The Internal Bus Interface monitors address and data buses for
programming information. The Internal Bus Interface also generates
Bus Request (BRQ) to request access to the address, data, and control
buses in response to a DMA Request (DRQ) from the SBX expansion
module. The CPU acknowledges BRQ with Bus Acknowledge
(BAK), signaling the Internal Bus Interface to generate DMA
Acknowledge (DAK) to the SBX expansion module and perform the
data transfer.
Address
Register
The Address register consists of a 20-bit base address and a 20-bit
current address. The base and current addresses are programmed with
the starting address of the memory block to be used in the transfer.
The memory is considered the source if the transfer is from ZT 8832
memory to the SBX expansion module. The memory is considered
the destination if the transfer is from the SBX expansion module to
the ZT 8832 memory. The current address is automatically adjusted
with hardware internal to the DCU as the transfers are made.
Address
Adjuster
The Address Adjuster automatically updates the current address
register each time a data transfer is completed. The address register is
incremented or decremented by one for each byte transfer.
9-5