Specifications

ILLUSTRATIONS
Figure 1–1 Functional Block Diagram. ........................... 1-5
Figure 2–1 STD ROM Jumper Configuration.
..................... 2-4
Figure 2–2 DOS MPX Jumper Configuration.
..................... 2-9
Figure 2–3 Local CPU Memory.
............................... 2-10
Figure 2–4 STD Bus CPU Memory.
............................ 2-11
Figure 2–5 STD Bus CPU I/O.
................................. 2-12
Figure 2–6 Local CPU I/O.
.................................... 2-13
Figure 3–1 STD Bus Control Port Architecture.
.................. 3-10
Figure 3–2 Local Control Port Architecture.
..................... 3-13
Figure 3–3 Board Select Port Architecture.
...................... 3-16
Figure 3–4 Interrupt Status Port Architecture.
.................... 3-18
Figure 5–1 V40 Block Diagram.
................................. 5-6
Figure 5–2 CPU Block Diagram.
................................ 5-7
Figure 5–3 Processor Status Word.
............................. 5-14
Figure 5–4 RESET and READY Synchronization.
................ 5-19
Figure 5–5 Memory Map.
..................................... 5-24
Figure 5–6 Data Formats.
...................................... 5-25
Figure 5–7 I/O Map.
.......................................... 5-26
Figure 5–8 Interrupt Processing.
................................ 5-29
Figure 6–1 On Chip Peripheral Connection Register.
............... 6-3
Figure 6–2 On Chip Peripheral Selection Register.
................. 6-4
Figure 6–3 Wait-Cycle 2 Register.
............................... 6-7
Figure 6–4 Wait-Cycle 1 Register.
............................... 6-8
Figure 6–5 Wait-Cycle Memory Boundary Register.
............... 6-9
Figure 6–6 Refresh Control Register.
........................... 6-10
Figure 6–7 Timer/Counter Clock Selection Register.
.............. 6-11
Figure 7–1 Counter/Timer Block Diagram.
....................... 7-4
Figure 7–2 Counter/Timer General Mode Register.
................ 7-9
Figure 7–3 Counter/Timer Count Mode Register.
................. 7-10
Figure 7–4 Counter/Timer Multiple Mode Register.
.............. 7-11
Figure 7–5 Counter/Timer Count Register.
...................... 7-12
Figure 7–6 Counter/Timer Status Register.
...................... 7-13
Figure 7–7 Mode 0 Operation.
................................. 7-16