Specifications

Interrupt Controller (V40)

Interrupt Masking

The ICU inputs are all maskable. The "clear interrupt" instruction can

be executed to disable all ICU inputs from generating interrupts. In

certain applications it may be necessary to disable, or mask, selected

ICU inputs. The ICU Interrupt Mask register (IMKW) includes one

bit for each ICU input to permit selective masking. An interrupt,

masked or not, flags a request by setting a bit in the IRQ register. If

the request is masked it is not passed to the IIS register until the mask

bit is cleared. If the interrupt input to the ICU is removed before the

mask bit is cleared, the IRQ bit is reset and the request is missed.

In certain instances it may be necessary to enable interrupts of a lower

priority than the one currently being serviced. The special mask mode

can be used to enable all levels of interrupts except the one being

serviced. The special mask mode is set and cleared using the IMDW

for the special mask mode. This is because the nonspecific FI will not

clear an IIS bit if it is masked. It is best to use the specific FI

command when operating in the special mask mode.

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